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TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
D
D
D
D
D
D
D
Reliable Silicon-Gate CMOS Technology
Low Power Consumption
– Operating Mode . . . 80 mW
– Power-Down Mode . . . 5 mW
µ-Law
Coding
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
No External Components Needed for
Sample, Hold, and Autozero Functions
Precision Internal Voltage Reference
Single Chip Contains A/D, D/A, and
Associated Filters
DW OR N PACKAGE
(TOP VIEW)
VBB
PWRO +
PWRO –
PDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
GSX
ANLG IN
ANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLK
FEATURES TABLE
Number of Pins:
16
Coding Law:
µ-Law
Variable Mode:
64 kHz to 2.048 MHz
Fixed Mode:
2.048 MHz (TCM29C18, TCM129C18),
1.536 MHz (TCM29C19, TCM129C19)
8-Bit Resolution
12-Bit Dynamic Range
description
The TCM29C18, TCM29C19, TCM129C18, and
TCM129C19 are low-cost single-chip PCM
codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices
incorporate both the A/D and D/A functions, an
antialiasing filter (A/D), and a smoothing filter
(D/A). They are ideal for use with the TMS320
DSP family members, particularly those featuring
a serial port such as the TMS32020, TMS32011,
and TMS320C25.
Primary applications include:
•
•
•
Digital encryption systems
Digital voice-band data storage systems
Digital signal processing
These devices are designed to perform encoding of analog input signals (A/D conversion) and decoding of
digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital
signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding,
and smoothing after decoding.
The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of 0°C to 70°C.
The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of
– 40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
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1
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
functional block diagram
Transmit Section
Autozero
11
ANLG IN
14
11
Filter
Sample
and Hold
and DAC
Comparator
Successive
Approximation
Output
Register
12
PCM OUT
TSX/
DCLKX
15
GSX
Reference
Analog-
to-Digital
Control
Logic
Control Section
Filter
Gain
Set
Σ
Buffer
Sample
and Hold
and DAC
Digital-
to-Analog
Control
Logic
6
Input
Register
5
PCM IN
DCLKR
Control
Logic
4
PDN
10
FSX/TSXE
9
CLK
Receive Section
PWRO+ 2
3
PWRO–
+
–
Reference
16
VCC
1
VBB
8
DGTL
GND
13
ANLG
GND
7
FSR/TSRE
2
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TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
Terminal Functions
TERMINAL
NAME
ANLG IN
ANLG GND
CLK
DCLKR
NO.
14
13
9
5
I
I
I/O
I
DESCRIPTION
Inverting analog input to uncommitted transmit operational amplifier.
Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND.
Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate
mode. CLK is used for both the transmit and receive sections.
Fixed-data-rate mode — variable-data-rate mode select. When DCLKR is connected to VBB, the device operates
in the fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate
mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz.
Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND.
I
Frame-synchronization clock input /time-slot enable for the receive channel. In the variable-data-rate mode, this
signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR
is TTL low for 30 ms.
Frame-synchronization clock input /time-slot enable for transmit channel. FSX/TSXE operates independently of,
but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300
ms.
Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit
filter.
Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock,
which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.
Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit
data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and
active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be
connected to a TTL high level.
Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly
in either a differential or single-ended configuration.
Inverting output of power amplifier. PWRO– is functionally identical to PWRO +.
Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain
output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the
transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.
Negative supply voltage. Input is – 5 V
±
5%.
Positive supply voltage. Input is 5 V
±
5%.
DGTL GND
FSR/TSRE
8
7
FSX/TSXE
10
I
GSX
PCM IN
PCM OUT
PDN
15
6
11
4
O
I
O
I
PWRO +
PWRO –
TSX/DCLKX
2
3
12
O
O
I/O
VBB
VCC
1
16
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3
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Output voltage range, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Input voltage range, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V
Operating free-air temperature range, T
A
: TCM29C18, TCM29C19 . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TCM129C18, TCM129C19 . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VBB.
recommended operating conditions (see Note 2)
MIN
VCC
VBB
VIH
VIL
VI(PP)
RL
CL
TA
Supply voltage (see Note 3)
Supply voltage
DGTL GND voltage with respect to ANLG GND
High-level input voltage, all inputs except ANLG IN
Low-level input voltage, all inputs except ANLG IN
Peak-to-peak analog input voltage (see Note 4)
Load resistance
Load capacitance
Operating free air temperature
free-air
GSX
PWRO + and/or PWRO –
GSX
PWRO + and/or PWRO –
TCM29C18 or TCM29C19
TCM129C18 or TCM129C19
0
– 40
10
300
50
100
70
85
2.2
0.8
4.2
4.75
– 4.75
NOM
5
–5
0
MAX
5.25
– 5.25
UNIT
V
V
V
V
V
V
kΩ
Ω
pF
°C
NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
3. Voltages at analog inputs and outputs and VCC and VBB terminals are with respect to ANLG GND. All other voltages are referenced
to DGTL GND unless otherwise noted.
4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct A/D conversion. The digital
code representing values higher than 4.2 V is 10 000 000. For values more negative than 4.2 V, the code is 0000000.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, f
DCLK
= 2.048 MHz, outputs not loaded
PARAMETER
Operating
ICC
Supply current from VCC
y
Standby
Power down
Operating
IBB
Supply current from VBB
Standby
Power down
FSX or FSR at VIL after 300 ms
PDN at VIL after 10
µs
FSX or FSR at VIL after 300 ms
PDN at VIL after 10
µs
TEST CONDITIONS
TCM29Cxx
MIN
MAX
10
1.2
1
– 10
– 1.2
–1
TCM129Cxx
MIN
MAX
14
1.5
1.2
– 14
– 1.5
– 1.2
mA
mA
UNIT
4
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