64K-bit/32K-bit 2-Wire Serial CMOS EEPROM
Preliminary
Description
TTE24C32/TTE24C64
The TTE24C32/TTE24C64 is an electrically erasable PROM device that uses the standard 2-wire interface for
communications. The TTE24C32/TTE24C64 contains a memory array of 32K-bits (4Kx8) and 64K-bits (8Kx8) repectively, and
each is further subdivided into 32 byte pages for Page-Write mode. This EEPROM is offered in wide operating voltages of
2.5V to 5.5V to be compatible with most application voltages. TT Semiconductor designed the TE24C32/TTE24C64 to be a
practical, low-power 2-wire EEPROM solution. The devices are packaged in 8-pin Ceramic DIP Flatpack, 20 Pin LCC and 8
,
pin Plastic DIp or SOIC.
The TTE24C32/TTE24C64 maintains compatibility with the popular 2-wire bus protocol, so it is easy to design into applications
implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the
TTE24C32/TTE24C64. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device, and a series of data, if appropriate. The TTE24C32/TTE24C64 has a Write
Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.
FEATURES
·
Two-Wire Serial Interface, I
2
C
TM
compatible
Bi-directional data transfer protocol
FEATURES
·
·
Self time write cycle with auto clear
-
5 ms @ 5.0V
Organization:
-24C32: 4Kx8 (128 pages of 32 bytes)
-24C64: 8Kx8 (256 pages of 32 bytes)
32 Byte Page Write Buffer
High Reliability
–Endurance: 100,000 Cycles
–Data Retention: 40 Years
Military and Extended temperature
ranges
·
400 KHz (2.5V) and 1 MHz (5.0V) compatibility
·
Low Power CMOS Technology
-Active Current less than 3 mA (5.0V)
-Stanby Current less than 6 µA (5.0V)
-
Standby Current less than 2 µA (2.5V)
·
Wide Voltage Operation
-Vcc = 2.5V to 5.5V
·
·
·
Hardware Data Protection
-Write
Protect Pin
·
Sequential Read Feature
·
Filtered Inputs for Noise Suppression
·
Pin
Name
A0
A1
A2
GND
SDA
SCL
WP
VCC
Function Block Diagram
REV. A
DIP, SOIC,
Flat Pack 8
Pin Package
1
2
3
4
5
6
7
8
LCC20
Pkg
5
6
7
10
15
16
17
20
Table 1. Pin Configurations
TT Semiconductor; 325 North Shepard Street; Anaheim, California 92806; USA
Tel: 1 714 257-2257; Fax: 1 714 257-2252; Web: www.ttsemiconductor.com
1
TT Semiconductor
Preliminary
TTE24C32/TTE24C64
DEVICE OPERATION
The
TTE24C32/TTE24C64
features
a
serial
communication and supports a bi-directional 2-wire
bus transmission protocol
called I
2
C
TM
.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA),
and a Serial Clock line (SCL). The protocol defines any
device that sends data onto the SDA bus as a
transmitter, and the receiving devices as receivers.
The bus is controlled by Master device which
generates the SCL, controls the bus access and
generates the Stop and Start conditions. The
TTE24C32/TTE24C64 is the Slave device on the bus.
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer
addresses and data into and out of the device. The
SDA pin is an open drain output and can be
wire-Ored with other open drain or open collector
outputs. The SDA bus requires a pullup resistor to Vcc.
The Bus Protocol:
–
Data transfer may be initiated only when the bus is
not
busy
– During a data transfer, the SDA line must remain
stable
whenever the SCL line is high. Any changes in the
data line while the SCL line is high will be interpreted as a
Start or Stop condition.
A0, A1, A2
The A0, A1 and A2 are the device address inputs that
are hardwired or left not connected for hardware
compatibility with the 24C16. When pins are
hardwired, as many as eight 32K/64K devices may
be addressed on a single bus system. When the pins
are not hardwired, the default values of A0, A1, and
A2 are zero.
WP
WP is the Write Protect pin. The input level determines
if all, or none of the array is protected from
modifications.
The state of the SDA line represents valid data after a
Start condition. The SDA line must be stable for the
duration of the High period of the clock signal. The
data on the SDA line may be changed during the
Low period of the clock signal. There is one clock
pulse per bit of data. Each data transfer is initiated
with a Start condition and terminated with a Stop
condition.
Start Condition
The Start condition precedes all commands to the
device and is defined as a High to Low transition of
SDA when
SCL is High. The TTE24C32/TTE24C64
monitors the SDA and SCL lines and will not respond
until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High
transition of SDA when SCL is High. All operations must
end with a Stop
condition.
2
TT Semicondutor; 325 North Shepard Street; Anaheim, California 92806; USA
Tel: 1 714 257-2257; Fax: 1 714 257-2252; Web: www.ttsemiconductor.com
REV. A
TTE24C32/TTE24C64
Acknowledge (ACK)
Preliminary
TT Semiconductor
After a successful data transfer, each receiving
device is required to generate an ACK. The
Acknowledging device pulls down the SDA line.
eight bits of data. The selected TTE24C32/TTE24C64
then prepares for a Read or Write operation by
monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the
Start
condition and the Slave address information
(with the R/W
set to Zero) to the Slave device. After the
Slave generates an ACK, the Master sends the two
byte address that are to
be written into the address
pointer of the TTE24C32/TTE24C64. After receiving
another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory
location.
The
TTE24C32/TTE24C64
acknowledges once more and the Master generates
the Stop condition, at which time the device begins
its internal programming cycle. While this internal
cycle is in progress, the device will not respond to any
request from the Master device.
Reset
The TTE24C32/TTE24C64 contains a reset function in
case the 2- wire bus transmission is accidentally
interrupted (eg. a power loss), or needs to be
terminated mid-stream. The reset is caused when the
Master device creates a Start condition. To do this, it
may be necessary for the Master device to monitor
the SDA line while cycling the SCL up to nine times.
(For each clock signal transition to High, the Master
checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
TTE24C32/TTE24C64 will enter standby mode: a) At
Power-up, and remain in it until SCL or SDA toggles; b)
Following the Stop signal if no write operation is
initiated; or c) Following any internal write operation
Page Write
The TTE24C32/TTE24C64 is capable of 32-byte
Page-Write operation.
A Page-Write is initiated in the
same manner as a Byte Write,but instead of
terminating the internal Write cycle after the first data
word is transferred, the Master device can transmit up
to 31 more bytes. After the receipt of each data
word, the TTE24C32/TTE24C64 responds immediately
with an ACK on SDA line, and the five lower order
data word address bits are internally incremented by
one, while the higher order bits of the data word
address remain constant. If a byte address is
incremented from the last byte of a page, it returns
to the first byte of that page. If the Master device
should transmit more than 32 words prior to issuing
the Stop condition, the address counter will “roll over,”
and the previously written data will be overwritten.
Once all 32 bytes are received and the Stop
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received
data is written to the TTE24C32/TTE24C64 in a single
Write cycle. All inputs are disabled until completion of
the internal Write cycle.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
device (Fig. 5) address is 8 bits. The four most
significant bits of the Slave device address are fixed
as 1010 for the TTE24C32/TTE24C64.
This device has three address bits (A2, A1, and A0),
which allows up to eight TTE24C32/TTE24C64 devices
to share the 2-wire bus. Upon receiving the Slave
address, the device compares the three address bits
with the hardwired A2, A1, and A0 input pins to
determine if it is the appropriate Slave.
The last bit of the Slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set
to 1, a Read operation is selected, and
when set to 0, a Write operation is selected.
After the Master transmits the Start condition and
Slave address byte (Fig. 5), the appropriate 2-wire
Slave (eg. TTE24C32/TTE24C64) will respond with ACK
on the SDA line. The Slave will pull down the SDA on
the ninth clock cycle, signaling that it received the
REV. A
TT Semiconductor; 325 North Shepard Street; Anaheim, California 92806; USA
Tel: 1 714 257-2257; Fax: 1 714 257-2252; Web: www.ttsemiconductor.com
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TT Semiconductor
Acknowledge (ACK) Polling
Preliminary
TTE24C32/TTE24C64
The disabling of the inputs can be used to take
advantage of the typical Write cycle time. Once the
Stop condition
is issued to indicate the end of the
host’s Write operation, the TTE24C32/TTE24C64
initiates the internal Write cycle. ACK polling can be
initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write
operation. If the TTE24C32/TTE24C64is still busy with
the Write operation, no ACK will be returned. If the
TTE24C32/TTE24C64 has completed the Write
operation, an ACK will be returned and the host can
then proceed with the next Read or Write operation.
TTE24C32/TTE24C64 acknowledges the word address,
the Master device resends the Start condition and the
Slave address, this time with the R/W bit set to one.
The TTE24C32/TTE24C64 then responds with its ACK
and sends the data requested. The Master device
does not send an ACK but will generate a Stop
condition. (Refer to Figure 9. Random Address Read
Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
TTE24C32/TTE24C64 sends the initial byte sequence,
the Master device now responds with an ACK
indicating it requires additional data from the
TTE24C32/TTE24C64.
The
TTE24C32/TTE24C64
continues to output data for each ACK received. The
Master device terminates the sequential Read
operation by pulling SDA High (no ACK) indicating the
last data word to be read, followed by a Stop
condition.
The data output is sequential, with the data from
address n followed by the data from address n+1, ...
etc. The address counter increments by one
automatically, allowing the entire memory contents
to be serially read during sequential Read operation.
When the memory address boundary of 8191 for
TTE24C64 or 4095 for TTE24C32 is reached, the
address counter “rolls over” to address 0, and the
TTE24C32/TTE24C64 continues to output data for
each ACK received. (Refer to Figure 10. Sequential
Read Operation Starting with a Random Address
Read Diagram.)
READ OPERATION
Read operations are initiated in the same manner as
Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation
options: current address read, random address read,
and sequential read.
Current Address Read
The TTE24C32/TTE24C64 contains an internal address
counter which maintains the address of the last byte
accessed, incremented by one. For example, if the
previous operation is either a Read or Write operation
addressed to the address location n, the internal
address counter would increment to address location
n+1. When the TTE24C32/TTE24C64 receives the
Slave Device Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit
the 8-bit data word stored at address location n+1.
The Master should not acknowledge the transfer but
should generate a Stop condition so the
TTE24C32/TTE24C64 discontinues transmission. If ‘n’ is
the last byte of the memory, the data from location
‘0’ will be transmitted. (Refer to Figure 8. Current
Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a
‘dummy’ Write operation by sending the Start
condition, Slave address and word address of the
location
it
wishes
to
read.
After
the
4
TT Semiconductor; 325 North Shepard Street; Anaheim, California 92806; USA
Tel: 1 714 257-2257; Fax: 1 714 257-2252; Web: www.ttsemiconductor.com
REV. A
TTE24C32/TTE24C64
Preliminary
1
TT Semiconductor
Ab so lute Maxi mum Rat ings (T
A
= 25°C)
Supply Voltage (V
S
)
Voltage on Any Pin (V
P
)
Temperature Under Bias (T
BIAS
)
+0.5 to +6.5 V
-0.5 to V
CC
+0.5 V
-55 to +175 °C
Storage Temperature (T
STG
)
Output Current (I
OUT
)
-65 to +200°C
5 mA
1.
Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational
sections of this specification is not implied. Exposure to these conditions for extended periods may affect reliability.
Rec om mended Op er at ing Con di tions
Parameter
Military
Extended Temp
Symbol
V
CC
V
CC
Conditions
-55 °C to +125 °C
-55 °C to +175 °C
Min
2.5
4.5
Typ
Max
5.5
5.5
Units
V
V
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Conditions
V
IN
= 0V
V
OUT
= 0V
1,2
Max
6
8
Units
pF
pF
1.
Tested initially and after any design or process changes that may affect these parameters.
2.
Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5.0V.
REV. A
TT Semiconductor; 325 North Shepard Street; Anaheim, California 92806; USA
Tel: 1 714 257-2257; Fax: +1 714 257-2252; Web: www.ttsemiconductor.com
5
