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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μ
PA2726UT1A
SWITCHING
N-CHANNEL POWER MOSFET
DESCRIPTION
The
μ
PA2726UT1A is N-channel MOSFET designed for DC/DC converter applications.
PACKAGE DRAWING (Unit: mm)
1.27
1
2
3
4
0.42
−0.05
+0.1
7
6
5
6
±0.2
5.4
±0.2
•
Low on-state resistance
R
DS(on)1
= 7.0 mΩ MAX. (V
GS
= 10 V, I
D
= 10 A)
R
DS(on)2
= 11.0 mΩ MAX. (V
GS
= 4.5 V, I
D
= 10 A)
•
Low input capacitance
C
iss
= 1720 pF TYP. (V
DS
= 15 V, V
GS
= 0 V)
•
Thin type surface mount package with heat spreader (8-pin HVSON)
•
RoHS Compliant
5.15
±0.2
5
±0.2
0.27
±0.05
1.0 MAX.
FEATURES
8
0.10 S
0.10 M
0
+0.05
−0
1
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note2
0.2
4.1
±0.2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
30
±20
±20
±120
1.5
4.6
150
−55
to
+150
20
40
V
V
A
A
W
W
°C
°C
A
mJ
1, 2, 3 : Source
4
: Gate
5, 6, 7, 8: Drain
3.65
±0.2
0.6
±0.15
0.7
±0.15
Total Power Dissipation
Channel Temperature
Storage Temperature
Total Power Dissipation (PW =10 sec)
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
I
AS
E
AS
EQUIVALENT CIRCUIT
Drain
THERMAL RESISTANCE
Channel to Ambient Thermal Resistance
Note2
R
th(ch-A)
R
th(ch-C)
83.3
1.5
°C/W
°C/W
Gate
Body
Diode
Channel to Case (Drain) Thermal Resistance
Notes 1.
PW
≤
10
μ
s, Duty Cycle
≤
1%
Source
2.
Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm
3.
Starting T
ch
= 25°C, V
DD
= 15 V, R
G
= 25
Ω,
V
GS
= 20
→
0 V, L = 100
μ
H
Remark
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G18299EJ1V0DS00 (1st edition)
Date Published April 2007 NS CP(K)
Printed in Japan
2006, 2007
μ
PA2726UT1A
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Note
Note
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
TEST CONDITIONS
V
DS
= 30 V, V
GS
= 0 V
V
GS
=
±
20 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 10 A
V
GS
= 10 V, I
D
= 10 A
V
GS
= 4.5 V, I
D
= 10 A
V
DS
= 15 V,
V
GS
= 0 V,
f = 1 MHz
V
DD
= 15 V, I
D
= 10 A,
V
GS
= 10 V,
R
G
= 10
Ω
MIN.
TYP.
MAX.
10
UNIT
μ
A
nA
V
S
±
100
1.5
7.5
5.6
8.0
1720
370
130
14
5.2
51
9.8
7.0
11.0
2.5
Drain to Source On-state Resistance
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Ω
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Gate Resistance
Note
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
R
G
V
DD
= 15 V,
V
GS
= 5 V,
I
D
= 20 A
I
F
= 20 A, V
GS
= 0 V
I
F
= 20 A, V
GS
= 0 V,
di/dt = 100 A/
μ
s
f = 1 MHz
15
5.0
4.9
0.82
30
23
1.6
Note
Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
R
L
V
DD
V
GS
V
GS
Wave Form
0
10%
V
GS
90%
V
DS
90%
90%
10%
10%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS
0
τ
τ
= 1
μ
s
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50
Ω
R
L
V
DD
2
Data Sheet G18299EJ1V0DS
μ
PA2726UT1A
TYPICAL CHARACTERISTICS (T
A
= 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
FORWARD BIAS SAFE OPERATING AREA
1000
I
D(pulse)
PW
1
i
0
dT - Percentage of Rated Power - %
100
I
D
- Drain Current - A
100
I
D(DC)
1
i
0
Po
w
m
s
i
=
30
0
80
60
40
20
0
0
20
40
60
80
100
120 140 160
μ
s
1
i
m
i
s
0
10
m
s
i
1
m
it e
Single Pulse
d
Mounted on a glass epoxy board of
25.4 mm x 25.4 mm x 0.8 mm
d
it e
m
Li V )
)
on
1
i
0
S(
=
D
R
GS
(V
er
D
1
i
0
s
is
si
pa
t io
n
Li
0.1
0.01
0.1
1
10
100
T
A
- Ambient Temperature -
°C
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
r
th(t)
- Transient Thermal Resistance -
°C/W
100
R
th(ch-A)
= 83.3°C/Wi
10
R
th(ch-C)
= 1.5°C/Wi
1
0.1
Single Pulse
R
th(ch-A)
: Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm
0.01
100
μ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
50
40
I
D
- Drain Current - A
10 V
4.5 V
4.0 V
Pulsed
3.8 V
50
40
I
D
- Drain Current - A
30
20
10
0
0
0.2
0.4
0.6
0.8
3.6 V
V
GS
= 3.0 V
3.2 V
3.4 V
30
20
10
0
T
A
=
−55°C
25°C
75°C
125°C
V
DS
= 10 V
Pulsed
0
1
2
3
4
5
1
V
DS
- Drain to Source Voltage - V
V
GS
- Gate to Source Voltage - V
Data Sheet G18299EJ1V0DS
3
