DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA2782GR
SWITCHING
N-CHANNEL POWER MOS FET/SCHOTTKY BARRIER DIODE
DESCRIPTION
The
µ
PA2782GR is N-Channel Power MOSFET, which built a
Schottky Barrier Diode inside.
This product is designed for synchronous DC/DC converter
application.
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8 ; Drain
FEATURES
•
Built a Schottky Barrier Diode
•
Low on-state resistance
R
DS(on)1
= 11 mΩ TYP. (V
GS
= 10 V, I
D
= 5.5 A)
R
DS(on)2
= 16 mΩ TYP. (V
GS
= 4.5 V, I
D
= 5.5 A)
R
DS(on)3
= 19 mΩ TYP. (V
GS
= 4.0 V, I
D
= 5.5 A)
•
Low C
iss
: C
iss
= 660 pF TYP.
•
Small and surface mount package (Power SOP8)
1
4
5.37 MAX.
+0.10
–0.05
6.0 ±0.3
4.4
0.8
1.8 MAX.
1.44
0.15
0.05 MIN.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
0.12 M
µ
PA2782GR
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C. All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
[MOSFET]
Drain Current (pulse)
Note1
Note2
EQUIVALENT CIRCUIT
Drain
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
30
±20
±11
±44
2.5
2
1
150
V
V
A
A
A
W
W
°C
°C
Gate
Protection
Diode
Source
Gate
Schottky
Diode
Average Forward Current
Total Power Dissipation
Total Power Dissipation
[SCHOTTKY]
I
F(AV)
P
T
P
T
T
ch
, T
j
Note3
Note3
[MOSFET]
[SCHOTTKY]
Channel & Junction Temperature
Storage Temperature
T
stg
−55
to + 150
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1%
2.
Rectangle wave, 50% Duty Cycle
2
3.
Mounted on ceramic substrate of 1200 mm x 2.2 mm
Caution Strong electric field, when exposed to this device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred.
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16421EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2002
µ
PA2782GR
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, unless other wise noted. All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Note
SYMBOL
I
DSS
TEST CONDITIONS
V
DS
= 24 V, V
GS
= 0 V
V
DS
= 24 V, V
GS
= 0 V, T
A
= 125°C
Gate Leakage Current
Gate Cut-off Voltage
Drain to Source On-state Resistance
Note
I
GSS
V
GS(off)
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Note
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
V
DD
= 15 V
V
GS
= 5 V
I
D
= 11 A
I
F
= 1 A, V
GS
= 0 V
I
F
= 1 A, V
GS
= 0 V, T
A
= 125°C
Reverse Recovery Time
Reverse Recovery Charge
t
rr
Q
rr
I
F
= 7 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
V
GS
=
±
20 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
GS
= 10 V, I
D
= 5.5 A
V
GS
= 4.5 V, I
D
= 5.5 A
V
GS
= 4.0 V, I
D
= 5.5 A
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= 15 V, I
D
= 5.5 A
V
GS
= 10 V
R
G
= 10
Ω
1.0
11
16
19
660
340
83
9
5
29
6
7.1
2.1
3.1
0.45
0.37
25
14
0.5
MIN.
TYP.
MAX.
50
10
±10
2.5
15
22.5
29
UNIT
µ
A
mA
µ
A
V
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
V
ns
nC
Note
Pulsed: PW
≤
350
µ
s, Duty Cycle
≤
2%
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
R
L
V
GS
PG.
R
G
Wave Form
D.U.T.
V
GS
0
10%
V
GS
90%
I
G
= 2 mA
50
Ω
R
L
V
DD
V
DD
PG.
90%
V
DS
90%
10%
10%
V
GS
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
2
Data Sheet G16421EJ1V0DS
µ
PA2782GR
TYPICAL CHARACTERISTICS (T
A
= 25°C. All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
dT - Percentage of Rated Power - %
120
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
P
T
- Total Power Dissipation - W
100
2.4
2
1.6
1.2
0.8
0.4
0
Mounted on ceramic substrate of
2
1200 mm x 2.2 mm
MOSFET
80
60
SCHOTTKY
40
20
0
0
25
50
75
100
125
150
175
0
20
40
60
80
100
120
140
160
T
A
- Ambient Temperature -
°C
T
A
- Ambient Temperature -
°C
FORWARD BIAS SAFE OPERATING AREA
100
I
D(pulse)
I
D(DC)
10
DC
1
R
DS(on)
Limited
(at V
GS
= 10 V)
100 ms
Power Dissipation Limited
0.1
Single pulse
Mounted on ceramic substrate of
2
1200 mm x 2.2 mm
0.01
0.01
0.1
1
10
100
10 ms
PW = 100
µs
1 ms
I
D
- Drain Current - A
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (MOSFET)
1000
R
th(t)
- Transient Thermal Resistance -
°C/W
100
R
th(ch-A)
= 62.5°C/W
10
1
Mounted on ceramic substrate of 1200 mm × 2.2 mm
Single pulse
0.1
1m
10 m
100 m
1
10
100
1000
2
PW - Pulse Width - s
Data Sheet G16421EJ1V0DS
3
µ
PA2782GR
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (SCHOTTKY)
1000
R
th(t)
- Transient Thermal Resistance -
°C/W
R
th(j-A)
= 125°C/W
100
10
1
Mounted on ceramic substrate of 1200 mm x 2.2 mm
Single pulse
2
0.1
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
50
Pulsed
45
3
V
DS
= 10 V
I
D
= 1 mA
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
GS(off)
- Gate Cut-off Voltage - V
I
D
- Drain Current - A
40
V
GS
= 10 V
35
30
25
20
15
10
5
0
0
0.5
1
1.5
2
4.5 V
2.5
2
4.0 V
1.5
1
0.5
0
- 50
0
50
100
150
V
DS
- Drain to Source Voltage - V
T
ch
- Channel Temperature -
°C
R
DS(on)
- Drain to Source On-state Resistance - mΩ
30
Pulsed
25
V
GS
= 4.0 V
4.5 V
15
10 V
10
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
30
Pulsed
25
20
20
15
I
D
= 5.5 A
10
5
5
0
0.1
1
10
100
0
0
5
10
15
20
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
4
Data Sheet G16421EJ1V0DS
µ
PA2782GR
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
40
Pulsed
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
C
iss
, C
oss
, C
rss
- Capacitance - pF
35
30
25
20
15
10 V
10
5
0
- 50
V
GS
= 4.0 V
4.5 V
V
GS
= 0 V
f = 1 MHz
1000
C
iss
C
oss
100
C
rss
0
50
100
150
10
0.01
0.1
1
10
100
T
ch
- Channel Temperature - °C
V
DS
- Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
1000
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
30
6
I
D
= 11 A
25
V
DD
= 24 V
15 V
6V
5
V
DS
- Drain to Source Voltage - V
V
DD
= 15 V
V
GS
= 10 V
R
G
= 10
Ω
100
20
V
GS
4
t
d(off)
10
t
d(on)
t
f
t
r
15
3
10
V
DS
5
2
1
1
0.1
1
10
100
0
0
2
4
6
8
0
I
D
- Drain Current - A
Q
G
- Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
100
100000
10000
1000
SOURCE TO DRAIN DIODE
REVERSE CURRENT
I
F
- Diode Forward Current - A
125°C
10
T
A
= 25°C
I
R
- Reverse Current -
µ
A
V
DS
= 30 V
100
10
1
0.1
0.01
- 50
24 V
1
V
GS
= 0 V
Pulsed
0.1
0
0.2
0.4
0.6
0.8
1
1.2
0
50
100
150
V
F(S-D)
- Source to Drain Voltage - V
T
j
- Junction Temperature - °C
Data Sheet G16421EJ1V0DS
5
V
GS
- Gate to Source Voltage - V
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
