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DATA SHEET

MOS INTEGRATED CIRCUIT

PD17240,17241,17242,17243,17244,17245,17246

4-BIT SINGLE-CHIP MICROCONTROLLERS

FOR SMALL GENERAL-PURPOSE INFRARED

REMOTE CONTROL TRANSMITTERS

DESCRIPTION

The

PD17240, 17241, 17242, 17243, 17244, 17245, 17246 (hereafter called the

PD17246 Subseries) are 4-

bit single-chip microcontrollers for small general-purpose infrared remote control transmitters.

This subseries employs 17K general-purpose register system architecture for the CPU, and can directly execute

operations between data memories instead of the conventional method of executing operations through an

accumulator. Moreover, all the instructions are 16-bit/1-word instructions, enabling efficient programming.

In addition, a one-time PROM model, the

PD17P246, to which data can be written only once, is also available.

This product is convenient either for evaluating the

PD17246 Subseries programs or for small-scale production of

application systems.

Detailed function descriptions are provided in the following user's manual. Be sure to read them before

designing.

PD172×× Subseries User's Manual: U12795E

FEATURES

• Infrared remote controller carrier generator (REM output)

• 17K architecture: General-purpose register system

• Program memory (ROM), data memory (RAM)

PD17240

Program

4 KB

447

4 bits

memory (ROM) (2,048

16)

Data memory

(RAM)

PD17241

8 KB

(4,096

16)

PD17242

12 KB

(6,144

16)

PD17243

16 KB

(8,192

16)

PD17244

20 KB

PD17245

24 KB

PD17246

32 KB

(10,240

16) (12,288

16) (16,384

16)

• 8-bit timer:

1 channel

• Basic interval timer/watchdog timer: 1 channel

• Instruction execution time (can be changed in two steps)

@ f

= 4 MHz:

• External interrupt pin (INT/P1B

• I/O pins:

• Supply voltage:

• On-chip RAM retention detector

• Low-voltage detector (mask option)

Unless otherwise specified, the

PD17246 is treated as the representative model throughout this document.

s (high-speed mode)/8

s (normal mode)

= 2.0 to 3.6 V

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. U15002EJ1V0DS00 (1st edition)

Date Published April 2003 N CP (K)

Printed in Japan

The mark

shows major revised points.

PD17240, 17241, 17242, 17243, 17244, 17245, 17246

APPLICATIONS

Preset remote controllers, toys, portable systems, etc.

ORDERING INFORMATION

Part Number

Package

30-pin plastic SSOP (7.62 mm (300))

PD17240MC-×××-5A4

PD17241MC-×××-5A4

PD17242MC-×××-5A4

PD17243MC-×××-5A4

PD17244MC-×××-5A4

PD17245MC-×××-5A4

PD17246MC-×××-5A4

Remark

×××

indicates ROM code suffix.

Data Sheet U15002EJ1V0DS

PD17240, 17241, 17242, 17243, 17244, 17245, 17246

DIFFERENCES BETWEEN

PD17246 SUBSERIES,

PD17236 SUBSERIES, AND

PD17255

SUBSERIES (1/2)

Item

ROM

PD17246 Subseries

PD17240:

PD17241:

PD17242:

PD17243:

PD17244:

PD17245:

PD17246:

447

4 bits

2,048

4,096

6,144

8,192

bits

PD17236 Subseries

PD17230:

PD17231:

PD17232:

PD17233:

PD17234:

PD17235:

PD17236:

223

4 bits

2,048

4,096

6,144

8,192

bits

PD17225 Subseries

PD17225:

PD17226:

PD17227:

PD17228:

2,048

4,096

6,144

8,192

bits

10,240

16 bits

12,288

16 bits

16,384

16 bits

10,240

16 bits

12,288

16 bits

16,384

16 bits

111

4 bits

(

PD17225, 17226)

223

4 bits

(

PD17227, 17228)

P0B

to P0B

: Input

P0C

to P0C

: Output

P0D

to P0D

: Output

RAM

Ports

P0B

to P0B

: I/O (bit I/O)

P0C

to P0C

: I/O (group I/O)

P0D

to P0D

: I/O (group I/O)

P1A

to P1A

: I/O (bit I/O)

P1B

: I/O, functions

alternately as INT pin

P0B

to P0B

: I/O (bit I/O)

P0C

to P0C

: I/O (group I/O)

P0D

to P0D

: I/O (group I/O)

P1A

: Input or output

selectable by mask

option

Reset

• Reset by watchdog

timer

• Reset by stack pointer

• Low-voltage detector

(mask option)

The RESET pin is internally pulled down by the occurrence of

the internal reset signals on the left, causing a reset (usually,

the RESET pin is pulled up).

A low level is output from the

WDOUT pin by the

occurrence of the internal

reset signals on the left, and

a reset takes place if the

WDOUT pin is externally

connected to the RESET pin.

Capacitor for oscillation

Vector address

Selected by mask option

(15 pF)

Basic interval timer: 0002H

Rising and falling

edges of INT pin:

0003H

8-bit timer:

0004H

Not provided

Basic interval timer:

0001H

Rising and falling edges of INT pin: 0002H

8-bit timer:

0003H

RAM retention flag

Provided

Not provided

Data Sheet U15002EJ1V0DS

PD17240, 17241, 17242, 17243, 17244, 17245, 17246

DIFFERENCES BETWEEN

PD17246 SUBSERIES,

PD17236 SUBSERIES, AND

PD17255

SUBSERIES (2/2)

Item

STOP mode release

condition

PD17246 Subseries

<1> When any of pins P0A

to P0A

goes low

<2> When pins P0B

to P0B

P0C

to P0C

, and P0D

PD17236 Subseries

PD17225 Subseries

<1> When any of pins P0A

When any of pins P0A

to P0A

goes low

P0A

and P0B

to P0B

goes

<2> When pins P0B

to P0B

, low

P0C

to P0C

, and P0D

to P0D

are used as input

to P0D

are used as

pins and when any of

input pins and when any

them goes low

of them goes low

<3> When an interrupt

request (IRQ) of the

interrupt for which the IP

flag is set is generated at

flag is set is generated

the rising edge or falling

at the rising edge or

edge of the INT pin

falling edge of the INT

<4> When P0E

to P0E

are

used as input pins when

a key matrix is used and

when any of these pins

goes low

<5> When P1A

to P1A

and

P1B

are used as input

pins when a key matrix is

used and when the level

of any of these pins

equals the set clear level

Carrier frequency

= 4 MHz)

Selected by register file

(after reset: f

/2)

<1> If carrier generation clock

is f

/2: 3.9 kHz to 1 MHz

<2> If carrier generation clock

is f

: 7.8 kHz to 2 MHz

<3> If carrier generation clock

is 2f

: 15.6 kHz to 4 MHz

NRZ low-level period

setting modulo register

(NRZLTMM) and NRZ

high-level period setting

modulo register

(NRZHTMM)

• NRZLTMM: 8 bits

(REM output control bit is bit

1 of register file at address

12H)

• NRZHTMM: 8 bits

• NRZLTMM: 7 bits (bit 7 is REM output control bit)

• NRZHTMM: 7 bits (bit 7 is fixed to 0)

Selected by mask option

<1> If carrier generation

clock is f

/2: 7.8 kHz to

1 MHz

<2> If carrier generation

clock is f

: 15.6 kHz to

2 MHz

7.8 kHz to 1 MHz

Data Sheet U15002EJ1V0DS

PD17240, 17241, 17242, 17243, 17244, 17245, 17246

PIN CONFIGURATION (TOP VIEW)

• 30-pin plastic SSOP (7.62 mm (300))

PD17240MC-×××-5A4, 17241MC-×××-5A4, 17242MC-×××-5A4, 17243MC-×××-5A4,

PD17244MC-×××-5A4, 17245MC-×××-5A4, 17246MC-×××-5A4

P0D

P1B

/INT

P0E

REM

OUT

GND

RESET

P1A

P0D

P0C

P0B

P0A

GND:

INT:

Ground

External interrupt request signal input

P0A

to P0A

: Input port (CMOS input with pull-up resistor)

P0B

to P0B

: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)

P0C

to P0C

: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)

P0D

to P0D

: I/O port (CMOS input with pull-up resistor/N-ch open-drain output)

P0E

to P0E

: I/O port (when key matrix is used: CMOS input with pull-up resistor/N-ch open-

drain output, when key matrix is not used: CMOS input/push-pull output)

P1A

/P1A

P1B

REM:

RESET:

, X

OUT

Input port (when key matrix is used: CMOS input/N-ch open-drain output, when

key matrix is not used: CMOS input/push-pull output)

Input port (CMOS input)

Remote controller output (CMOS push-pull output)

Reset input

Power supply

Resonator connection

Data Sheet U15002EJ1V0DS