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USB97C100QFP

USB Bus Controller, CMOS, PQFP128, QFP-128

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:SMSC

厂商官网:http://www.smsc.com/

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
零件包装代码
QFP
包装说明
FQFP, QFP128,.67X.93,20
针数
128
Reach Compliance Code
unknown
地址总线宽度
20
总线兼容性
ISA
最大时钟频率
24 MHz
最大数据传输速率
12 MBps
外部数据总线宽度
8
JESD-30 代码
R-PQFP-G128
JESD-609代码
e0
长度
20 mm
端子数量
128
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
FQFP
封装等效代码
QFP128,.67X.93,20
封装形状
RECTANGULAR
封装形式
FLATPACK, FINE PITCH
峰值回流温度(摄氏度)
235
电源
3.3/5 V
认证状态
Not Qualified
座面最大高度
3.4 mm
最大压摆率
63 mA
最大供电电压
3.63 V
最小供电电压
2.97 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
uPs/uCs/外围集成电路类型
BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches
1
文档预览
USB97C100
ADVANCE INFORMATION
Multi-Endpoint USB Peripheral Controller
FEATURES
High Performance USB Peripheral Controller
Engine
-
Integrated USB Transceiver
-
Serial Interface Engine (SIE)
-
8051 Microcontroller (MCU)
-
Patented Memory Management Unit (MMU)
-
4 Channel 8237 DMA Controller
(ISADMA)
-
4K Byte On Board USB Packet Buffer
-
Quasi-ISA Peripheral Interface
-
USB Bus Snooping Capabilities
-
GPIOs
Complete USB Specification 1.1 Compatibility
-
Isochronous, Bulk, Interrupt, and Control
Data Independently Configurable per
Endpoint
-
Dynamic Hardware Allocation of -Packet
Buffer for Virtual Endpoints
-
Multiple Virtual Endpoints (up to 16 TX, 16
RX Simultaneously)
-
Multiple Alternate Address Filters
-
Dynamic Endpoint Buffer Length
Allocation (0-1280 Byte Packets)
High Speed (12Mbps) Capability
MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
-
128 Byte Page Size
-
10 Pages Maximum per Packet
-
Up to 16 Deep Receive Packet Queue
-
Up to 5 Deep Transmit Packet Queue, per
Endpoint
-
Hardware Generated Packet Header
Records Each Packet Status Automatically
-
Simultaneous Arbitration Between MCU,
SIE, and ISA DMA Accesses
Extended Power Management
-
Standard 8051 "Stop Clock" Modes
-
Additional USB and ISA Suspend
Resume Events
-
Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
-
24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
-
Independent Clock/Power Management for
SIE, MMU, DMA and MCU
DMA Capability with ISA Memory
-
Four Independent Channels
-
Transfer Between Internal and External
Memory
-
Transfer Between I/O and Buffer Memory
-
External Bus Master Capable
External MCU Memory Interface
-
1M Byte Code and Data Storage via 16K
Windows
-
Flash, SRAM, or EPROM
-
Downloadable via USB, Serial Port, or ISA
Peripheral
Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
-
1M ISA Memory Space via 4K MCU Window
-
64K ISA I/O Space via 256 Byte MCU
Window
-
4 External Interrupt Inputs
-
4 DMA Channels
-
Variable Cycle Timing
-
8 Bit Data Path
5V or
3.3v
Operation
On Board Crystal Driver Circuit
128 Pin QFP Package
ORDERING INFORMATION
Order Number: USB97C100QFP
128 Pin QFP Package
SMSC DS – USB97C100
Rev. 01/03/2001
GENERAL DESCRIPTION
The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple
endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to
be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput
disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall
bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing back-
to-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to coexist with
other peripherals such as serial and parallel ports on a single USB link.
The USB97C100 allows external program code to be downloaded over the USB to allow easy implementation of varied
peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades and
modifications.
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2001
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS – USB97C100
Page 2
Rev. 01/03/2001
TABLE OF CONTENTS
FEATURES ................................................................................................................................................................... 1
GENERAL DESCRIPTION............................................................................................................................................ 2
PIN CONFIGURATION ................................................................................................................................................. 4
DESCRIPTION OF PIN FUNCTIONS ........................................................................................................................... 5
BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7
FUNCTIONAL DESCRIPTION...................................................................................................................................... 9
Serial Interface Engine (SIE)......................................................................................................................................... 9
Micro Controller Unit (MCU) .......................................................................................................................................... 9
SIEDMA......................................................................................................................................................................... 9
Memory Management Unit (MMU) Register Description ............................................................................................... 9
ISADMA......................................................................................................................................................................... 9
Applications ................................................................................................................................................................. 10
TYPICAL SIGNAL CONNECTIONS ............................................................................................................................ 12
MCU MEMORY MAP .................................................................................................................................................. 13
Code Space................................................................................................................................................................. 13
Data Space.................................................................................................................................................................. 13
ISADMA Memory Map ................................................................................................................................................. 13
MCU Block Register Summary.................................................................................................................................... 14
MMU Block Register Summary ................................................................................................................................... 15
SIE Block Register Summary ...................................................................................................................................... 16
MCU REGISTER DESCRIPTION................................................................................................................................ 17
MCU Runtime Registers.............................................................................................................................................. 17
FIFO Status Registers................................................................................................................................................. 20
MCU Power Management Registers ........................................................................................................................... 24
MCU ISA Interface Registers ...................................................................................................................................... 27
8237 (ISADMA) REGISTER DESCRIPTION .............................................................................................................. 30
Memory Map................................................................................................................................................................ 30
Runtime Registers....................................................................................................................................................... 31
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION ....................................................................... 37
MMU Interface Registers............................................................................................................................................. 37
MMU FREE PAGES REGISTER................................................................................................................................. 40
16 BYTE DEEP TX COMPLETION FIFO REGISTER ................................................................................................ 40
TX FIFO POP REGISTER........................................................................................................................................... 41
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ............................................................................. 45
Packet Header Definition............................................................................................................................................. 45
SIE Interface Registers ............................................................................................................................................... 46
DC PARAMETERS ..................................................................................................................................................... 51
USB PARAMETERS ................................................................................................................................................... 53
USB DC PARAMETERS ............................................................................................................................................. 53
USB AC PARAMETERS.............................................................................................................................................. 54
MECHANICAL OUTLINE............................................................................................................................................ 63
USB97C100 REVISIONS............................................................................................................................................ 64
SMSC DS – USB97C100
Page 3
Rev. 01/03/2001
PIN CONFIGURATION
SA11
SA12
nMEMW
nMEMR
nIOR
nIOW
AEN
VCC
SD0
SD1
SD2
SD3
GND
SD4
SD5
SD6
SD7
nDACK0
DRQ0
nDACK1
DRQ1
nDACK2
DRQ2
nDACK3
DRQ3
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
SA10
SA9
SA8
SA7
SA6
SA5
SA4
GND
SA3
SA2
SA1
SA0
SA13
SA14
SA15
SA16
SA17
SA18
SA19
GND
IRQ3
IRQ2
IRQ1
IRQ0
VCC
nTEST
PWRGD
RESET_IN
TST_OUT
XTAL1
XTAL2
GND
CLKOUT
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
TC
nMASTER
VCC
READY
EXTCLK
FALE
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
USBD+
VCC3.3
USBD-
VCC
FA19
FA18
FA11
FA9
FA8
FA13
FA14
FA17
GND
nFWR
FA16
USB97C100
nFRD
FA10
nFCE
FD7
FD6
FD5
FD4
FD3
FA0
FA1
GPIO5
GPIO6
GPIO7
FA2
VCC
FA3
FA4
FA5
FA6
FA7
FA12
FIGURE 1 - PIN CONFIGURATION
SMSC DS – USB97C100
Page 4
FA15
FD1
FD0
GND
FD2
62
63
64
65
Rev. 01/03/2001
DESCRIPTION OF PIN FUNCTIONS
Table 1 - USB97C100 Pin Configuration
QFP PIN
NUMBER
100
SYMBOL
READY
PIN DESCRIPTION
ISA INTERFACE
Channel is ready when high.
ISA memory or slave devices use this signal to lengthen a bus
cycle from the default time. Extending the length of the bus
cycle can only be done when the bus cycles are derived from
the Internal DMA controller core. 8051 MCU generated Memory
or I/O accesses cannot and will not be extended even if
READY is asserted low by an external ISA slave device. The
external slave device negates this signal after decoding a valid
address and sampling the command signals (nIOW, nIOR,
nMEMW, and nMEMR). When the slave’s access has
completed, this signal should be allowed to float high.
DMA Request channels 3-0; active high.
These signals are used to request DMA service from the DMA
controller. The requesting device must hold the request signal
until the DMA controller drives the appropriate DMA
acknowledge signal (nDACK[3:0]).
DMA Acknowledge channels 3-0; active low.
These signals are used to indicate to the DMA requesting
device that it has been granted the ISA bus.
DMA Terminal Count; active high.
This signal is used to indicate that a DMA transfer has
completed.
System Address Bus
These signals address memory or I/O devices on the ISA bus.
System Data Bus
These signals are used to transfer data between system
devices.
Address Enable
This signal indicates address validation to I/O devices. When
low this signal indicates that an I/O slave may respond to
addresses and I/O commands on the bus. This signal is high
during DMA cycles to prevent I/O slaves from interpreting DMA
cycles as valid I/O cycles.
I/O Write; active low.
This signal indicates to the addressed ISA I/O slave to latch
data from the ISA bus.
I/O Read; active low.
This signal indicates to the addressed ISA I/O slave to drive
data on the ISA bus.
Memory read; active low
This signal indicates to the addressed ISA memory slave to
drive data on the ISA bus.
126
nMEMW
Memory write; active low
This signal indicates to the addressed ISA memory slave to
latch data from the ISA bus.
O8
BUFFER
TYPE
IP
104, 106,
108, 110
DRQ[3:0]
I
105, 107,
109, 111
103
nDACK
[3:0]
TC
O8
O8
19-13,
127-7,
9-12
112-115,
117-120
122
SA[19:0]
O8
SD[7:0]
I/O8
AEN
O8
123
nIOW
O8
124
nIOR
O8
125
nMEMR
O8
SMSC DS – USB97C100
Page 5
Rev. 01/03/2001
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