UT54ACS164245S/SE
Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
July 2010
www.aeroflex.com/16bitlogic
FEATURES
•
Voltage translation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
•
Cold sparing
- 1MΩ minimum input impedance power-off
• 0.6μm
CRH CMOS Technology
•
Operational Environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
•
High speed, low power consumption
•
Schmitt trigger inputs to filter noisy signals
•
Available QML Q or V processes
•
Standard Microcircuit Drawing 5962-98580
- Device types 01, 02, 03, 04, 05
•
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACS164245S MultiPurpose transceiver
is built using Aeroflex’s CMOS technology and is ideal for
space applications. This high speed, low power
UT54ACS164245S transceiver is designed to perform multiple
functions including: asynchronous two-way communication,
signal buffering, voltage translation, and cold sparing. With
V
DD
equal to zero volts, the UT54ACS164245S outputs and
inputs present a minimum impedance of 1MΩ making it ideal
for "cold spare" applications. Balanced outputs and low "on"
output impedance make the UT54ACS164245S well suited for
driving high capacitance loads and low impedance backplanes.
The UT54ACS164245S enables system designers to interface
3.3 volt CMOS compatible components with 5 volt CMOS com-
ponents. For voltage translation, the A port interfaces with the
3.3 volt bus; the B port interfaces with the 5 volt bus. The
direction control (DIRx) controls the direction of data flow. The
output enable (OEx) overrides the direction control and disables
both ports. These signals can be driven from either port A or
B. The direction and output enable controls operate these de-
vices as either two independent 8-bit transceivers or one 16-bit
transceiver.
1
LOGIC SYMBOL
OE1 (48)
OE2 (25)
(1)
DIR1
(47)
(46)
(44)
G1
G2
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
11
12
(24)
DIR2
1A1
1A2
1A3
(2)
(3)
(5)
(6)
(8)
1B1
1B2
1B3
1B4
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
2A2
2A3
(35)
(33)
21
22
1B5
(9)
1B6
(11)
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
PIN DESCRIPTION
Pin Names
OEx
DIRx
xAx
xBx
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (3.3V Port)
Side B Inputs or 3-State Outputs (5V Port)
PINOUTS
POWER TABLE
1
Port B
5 Volts
5 Volts
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port B Cold Spare
48-Lead Flatpack
Top View
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
OE2
3.3 Volts
V
SS
V
SS
NOTE:
1. V
DD2
cannot be tied to V
SS
while power is applied to V
DD1
.
I/O Guidelines
Control signals DIRx and /OEx are 5 volt tolerant inputs. When
VDD2 is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can
be applied to all control inputs. Additionally, it is recommended
that all unused inputs be tied to VSS through a 1KΩ to 10KΩ
resistor. It's good design practice to tie the unused input to VSS
via a resistor to reduce noise susceptibility. The resistor protects
the input pin by limiting the current from high going variations
in VSS. The number of inputs that can be tied to the resistor pull-
down can vary. It is up to the system designer to choose how
many inputs are tied together by figuring out the max load the
part can drive while still meeting system performance specs. In-
put signal transitions should be driven to the device with a rise
and fall time that is <100ms.
Power Application Guidelines
For proper operation connect power to all VDD and ground all
VSS pins (i.e., no floating VDD or VSS input pins). If VDD1
and VDD2 are not powered up together, then VDD2 should be
powered up first for proper control of /OEx and DIRx. Until
VDD2 reaches 2.75V + 5%, control of the outputs by OE and
DIR cannot be guaranteed. During operation of the part, after
power up, insure VDD1 > VDD2.
Power Up
The direction control (DIRx) and output enable (/OEx) for
the UT54ACS164245S/SE will only function properly if
VDD2, PortA, (3.3V) is powered up before VDD1, PortB,
(5.0V). The circuitry that powers /OEx and DIRx is powered
internally from the VDD2 supply, as illustrated in
Figure S/SE Planes. If this sequence is not followed there
is no way to guarantee the state of /OEx and /DIR if VDD1
was powered up before VDD2. After power up VDD1
must be greater than or equal to VDD2. However VDD2
can not be connected to VSS while VDD1 is powered.
2
Figure S/SE Planes
Internal connection of ports and power s supplies
VDD1
VDD2
DIR1
OE1
DIR2
OE2
PORTA
Enable/
Direction
Control
Logic
Enable/
Direction
Control
Logic
PORTB
CORE
Power Down
The proper power down sequence for the
UT54AC164245SE requires that outputs on both Port A
and Port B be disabled first,
1) /OEx high
2) Next power down VDD1
3) Then power down VDD2
FUNCTION TABLE
ENABLE
OEx
L
L
H
DIRECTION
DIRx
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
4
LOGIC DIAGRAM
DIR1
(1)
(48)
OE1
DIR2
(24)
(25)
OE2
1A1
(47)
(2)
1B1
2A1
(36)
(13)
2B1
1A2
(46)
(3)
1B2
2A2
(35)
(14)
2B2
1A3
(44)
(5)
1B3
2A3
(33)
(16)
2B3
3.3V PORT
3.3V PORT
1A4
(43)
2A4
(32)
(17)
2B4
5 V PORT
(6)
1A5
(41)
(8)
1A6
(40)
(9)
1A7
(38)
(11)
1A8
(37)
(12)
1B4
2A5
(30)
(19)
2B5
1B5
2A6
1B6
2A7
1B7
2A8
1B8
(26)
(27)
(29)
(20)
2B6
(22)
2B7
(23)
2B8
5
5 V PORT
