V58C2256(804/404/164)S
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
PRELIMINARY
Features
■
High speed data transfer rates with system frequency
up to 200 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 66-pin 400 mil TSOP or 60 Ball SOC BGA
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V
■
Power Supply 2.6V ± 0.1V for DDR400
■
QFC options for FET control. x4 parts.
*Note: (-5B) Supports PC3200 module with 2.5-3-3 timing
(-5) Supports PC3200 module with 3-3-3 timing
(-5C) Supports PC3200 module with 3-4-4 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-7) Supports PC2100 module with 2-2-2 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
(-8) Supports PC1600 module with 2-2-2 timing
CILETIV LESO M
5B
DDR400A
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
7.5 ns
5ns
5ns
200 MHz
5
DDR400A
7.5 ns
6ns
5ns
200 MHz
6
DDR333B
7.5 ns
6 ns
-
166 MHz
7
DDR266A
7.5ns
7ns
-
143 MHz
75
DDR266B
10 ns
7.5 ns
-
133 MHz
8
DDR200
10 ns
8 ns
-
125 MHz
Description
The V58C2256(804/404/164)S is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)S achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are ocurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 SOC BGA
•
CK Cycle Time (ns)
-5B
•
Power
-75
•
-5
•
-6
•
-7
•
-8
•
Std.
•
L
•
Temperature
Mark
Blank
V58C2256(804/404/164)S Rev.1.9 March 2003
1
V58C2256(804/404/164)S
CILETIV LESO M
60-Ball SOC BGA PIN OUT
(x4)
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ3
NC
DQ2
DQS
DM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ0
NC
DQ1
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
(x8)
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
X4 Device Ball Pattern
X8 Device Ball Pattern
(x16)
1
2
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ2
DQ4
DQ6
8
DQ0
VSSQ
VDDQ
VSSQ
9
PIN A1 INDEX
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
7
8
9
LDQS VDDQ
LDM
WE
RAS
BA1
A0
A2
VDD
VDD
CAS
CS
BA0
A10/AP
A1
A3
X16 Device Ball Pattern
TOP VIEW
(See the ball through the package)
V58C2256(804/404/164)S Rev. 1.9 March 2003
2
V58C2256(804/404/164)S
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
8Mb x 16
16Mb x 8
32Mb x 4
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
12
BA0, BA1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V
SS
V
DDQ
V
SSQ
NC
VREF
DQ’s
DM (UDM, LDM)
V
DD
Data Input/Output
Data Mask
Power
(+2.5V and +2.6V for DDR400)
Ground
Power for I/O’s
(+2.5V and +2.6V for DDR400)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
FET Control
CILETIV LESO M
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
66 PIN TSOP (II)
13
(400mil x 875 mil)
14
15
Bank Address
BA0-BA1
16
17
Row Address
18
A0-A12
19
20
Auto Precharge
A10
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
5
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
QFC/NC QFC/NC QFC/NC
NC
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V58C2256(804/404/164)S Rev. 1.9 March 2003
3
QFC
V58C2256(804/404/164)S
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
V58C2256(804/404/164)S Rev. 1.9 March 2003
4
QFC
CAS
RAS
WE
DM
CK
CK
CS
CILETIV LESO M
V
MOSEL VITELIC
MANUFACTURED
58
C
2 256(80/40/16) 4
S
X T XX
DDR SDRAM
CMOS
2.5V
2.6V for DDR400
256Mb, 8K Refresh
x8, x4, x16
4 Banks
SPEED
5B (200MHz@2.5-3-3)
5 (200MHz@3-3-3)
5C (200MHz@3-4-4)
6 (133MHz@2.5-3-3)
7 (143MHz@2-3-3)
75(133MHz@2.5-3-3)
COMPONENT
PACKAGE, T = TSOP S=SOC BGA 8 (125MHz@2-2-2)
COMPONENT
REV LEVEL A=0.14u
SSTL
Block Diagram
Column Addresses
64M x 4
Row Addresses
A0 - A12, BA0, BA1
A0 - A9, A11, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
8192 x 1024
x8
8192 x 1024
x8
8192 x 1024
x8
8192 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
V58C2256(804/404/164)S
Block Diagram
Column Addresses
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
RAS
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
V58C2256(804/404/164)S Rev. 1.9 March 2003
5
QFC
CAS
WE
DM
CK
CK
CS
CILETIV LESO M
32M x 8
Row Addresses
A0 - A12, BA0, BA1
A0 - A9, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
8192 x 512
x 16 bit
8192 x 512
x 16 bit
8192 x 512
x 16bit
8192 x 512
x 16bit
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
7
51单片机
