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V58C2256(804/404/164)S

HIGH PERFORMANCE

2.5 VOLT 256 Mbit DDR SDRAM

4 BANKS X 8Mbit X 8 (804)

4 BANKS X 4Mbit X 16 (164)

4 BANKS X 16Mbit X 4 (404)

DDR333B

DDR266A

7.5ns

7ns

143 MHz

DDR266B

10 ns

7.5 ns

133 MHz

PRELIMINARY

Features

■

High speed data transfer rates with system

frequency up to 166 MHz

■

Data Mask for Write Control

■

Four Banks controlled by BA0 & BA1

■

Programmable CAS Latency: 2, 2.5

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 8192 cycles/64 ms

■

Available in 66-pin 400 mil TSOP or 60 Ball SOC

BGA

■

SSTL-2 Compatible I/Os

■

Double Data Rate (DDR)

■

Bidirectional Data Strobe (DQS) for input and

output data, active on both edges

■

On-Chip DLL aligns DQ and DQs transitions with

CK transitions

■

Differential clock inputs CK and CK

■

Power Supply 2.5V ± 0.2V

■

QFC options for FET control. x4 parts.

*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing

DDR 266A Supports PC2100 module with 2-2-2 timing

DDR 266B Supports PC2100 module with 2.5-3-3 timing

DDR 200 Supports PC1600 module with 2-2-2 timing

CILETIV LESO M

DDR200

10 ns

8 ns

125 MHz

Clock Cycle Time (t

CK2

)

Clock Cycle Time (t

CK2.5

)

System Frequency (f

CK max

)

7.5 ns

6 ns

166 MHz

Description

The V58C2256(804/404/164)S is a four bank

DDR DRAM organized as 4 banks x 8Mbit x 8 (804),

4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4

(404). The V58C2256(804/404/164)S achieves high

speed data transfer rates by employing a chip archi-

tecture that prefetches multiple bits and then syn-

chronizes the output data to a system clock.

All of the control, address, circuits are synchro-

nized with the positive edge of an externally sup-

plied clock. I/O transactions are ocurring on both

edges of DQS.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate is pos-

sible depending on burst length, CAS latency and

speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

JEDEC 66 TSOP II

60 SOC BGA

•

CK Cycle Time (ns)

-6

•

Power

-8

•

-7

•

-75

•

Std.

•

Temperature

Mark

Blank

V58C2256(804/404/164)S Rev.1.4 October 2002

V58C2256(804/404/164)S

CILETIV LESO M

60-Ball SOC BGA PIN OUT

(x4)

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A12

A11

VSS

DQ3

DQ2

DQS

CKE

VSS

VDD

DQ0

DQ1

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

(x8)

VSSQ

VREF

DQ7

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A12

A11

VSS

DQ6

DQ5

DQ4

DQS

CKE

VSS

VDD

DQ1

DQ2

DQ3

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

X4 Device Ball Pattern

X8 Device Ball Pattern

(x16)

DQ15

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A12

A11

VSS

DQ13

DQ11

DQ9

UDQS

UDM

CKE

VSS

VDD

DQ2

DQ4

DQ6

DQ0

VSSQ

VDDQ

VSSQ

PIN A1 INDEX

VDDQ

DQ1

DQ3

DQ5

DQ7

VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

LDQS VDDQ

LDM

RAS

BA1

VDD

CAS

BA0

A10/AP

X16 Device Ball Pattern

TOP VIEW

(See the ball through the package)

V58C2256(804/404/164)S Rev. 1.4 October 2002

V58C2256(804/404/164)S

66 Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

8Mb x 16

16Mb x 8

32Mb x 4

Pin Names

CK, CK

CKE

RAS

CAS

DQS (UDQS, LDQS)

–A

BA0, BA1

Differential Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Data Strobe (Bidirectional)

Address Inputs

Bank Select

DQ’s

DM (UDM, LDM)

DDQ

SSQ

VREF

QFC

Data Input/Output

Data Mask

Power (+2.5V)

Ground

Power for I/O’s (+2.5V)

Ground for I/O’s

Not connected

Reference Voltage for Inputs

FET Control

CILETIV LESO M

DDQ

SSQ

DDQ

SSQ

DDQ

LDQS

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

66 PIN TSOP (II)

(400mil x 875 mil)

Bank Address

BA0-BA1

Row Address

A0-A12

Auto Precharge

A10

SSQ

DDQ

SSQ

DDQ

SSQ

DQS

REF

CKE

SSQ

DDQ

SSQ

DDQ

SSQ

DQS

REF

CKE

SSQ

DDQ

SSQ

DDQ

SSQ

UDQS

REF

UDM

CKE

QFC/NC QFC/NC QFC/NC

LDM

CAS

RAS

AP/A

CAS

RAS

AP/A

CAS

RAS

AP/A

V58C2256(804/404/164)S Rev. 1.4 October 2002

V58C2256(804/404/164)S

Column decoder

Sense amplifier & I(O) bus

Column decoder

Sense amplifier & I(O) bus

Column decoder

Sense amplifier & I(O) bus

Bank 0

Bank 1

Bank 2

Column decoder

Sense amplifier & I(O) bus

CKE

CK, CK

DLL

Strobe

Gen.

Data Strobe

DQS

V58C2256(804/404/164)S Rev. 1.4 October 2002

QFC

CAS

RAS

CILETIV LESO M

MOSEL VITELIC

MANUFACTURED

2 256(80/40/16) 4

X T XX

DDR SDRAM

CMOS

2.5V

256Mb, 8K Refresh

x8, x4, x16

4 Banks

SSTL

SPEED

6 (133MHz@CL2.5))

7 (143MHz@CL2.5))

75(133MHz@CL2.5)

8 (125MHz@CL2.5)

COMPONENT

PACKAGE, T = TSOP S=SOC BGA

COMPONENT

REV LEVEL A=0.14u

Block Diagram

Column Addresses

64M x 4

Row Addresses

A0 - A12, BA0, BA1

A0 - A9, A11, AP, BA0, BA1

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

Row decoder

Memory array

Row decoder

Memory array

Row decoder

Memory array

Row decoder

Memory array

Bank 3

8192 x 1024

Input buffer

Output buffer

Control logic & timing generator

-DQ

V58C2256(804/404/164)S

Block Diagram

Column Addresses

Column decoder

Sense amplifier & I(O) bus

Column decoder

Sense amplifier & I(O) bus

Column decoder

Sense amplifier & I(O) bus

Bank 0

Bank 1

Bank 2

Column decoder

Sense amplifier & I(O) bus

CKE

RAS

CK, CK

DLL

Strobe

Gen.

Data Strobe

DQS

V58C2256(804/404/164)S Rev. 1.4 October 2002

QFC

CAS

CILETIV LESO M

32M x 8

Row Addresses

A0 - A12, BA0, BA1

A0 - A9, AP, BA0, BA1

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

Row decoder

Memory array

Row decoder

Memory array

Row decoder

Memory array

Row decoder

Memory array

Bank 3

8192 x 512

x 16 bit

8192 x 512

x 16 bit

8192 x 512

x 16bit

8192 x 512

x 16bit

Input buffer

Output buffer

Control logic & timing generator

-DQ

参数对比

与V58C2256804SXT75相近的元器件有：V58C2256164SXT75、V58C2256164SXT7、V58C2256404SXT6、V58C2256404SXT7、V58C2256804SXT8、V58C2256164SXT6。描述及对比如下：

型号	V58C2256804SXT75	V58C2256164SXT75	V58C2256164SXT7	V58C2256404SXT6	V58C2256404SXT7	V58C2256804SXT8	V58C2256164SXT6
描述	DDR DRAM, 32MX8, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 16MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 16MX16, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 64MX4, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 64MX4, 0.75ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 32MX8, 0.8ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66	DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, PLASTIC, TSOP2-66
零件包装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
包装说明	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,
针数	66	66	66	66	66	66	66
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	0.75 ns	0.75 ns	0.75 ns	0.7 ns	0.75 ns	0.8 ns	0.7 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 代码	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
长度	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
内存密度	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	8	16	16	4	4	8	16
功能数量	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1
端子数量	66	66	66	66	66	66	66
字数	33554432 words	16777216 words	16777216 words	67108864 words	67108864 words	33554432 words	16777216 words
字数代码	32000000	16000000	16000000	64000000	64000000	32000000	16000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	32MX8	16MX16	16MX16	64MX4	64MX4	32MX8	16MX16
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )	-	-	Mosel Vitelic Corporation ( MVC )	Mosel Vitelic Corporation ( MVC )
Base Number Matches	1	1	1	1	1	-	-