V827464N24SC
2.5 VOLT 64M x 72 HIGH PERFORMANCE
REGISTERED ECC DDR SDRAM MODULE
Features
■
184 Pin Registered 67,108,864 x 72 bit
Organization DDR SDRAM Modules
■
Utilizes High Performance 64M x 4 DDR
SDRAM in TSOPII-66 and FBGA Package
■
Single +2.5V (± 0.2V) Power Supply
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8192 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
DDR SDRAM Performance
Component Used
t
CK
Description
The V827464N24SC memory module is
organized 67,108,864 x 72 bits in a 184 pin memory
module. The 64M x 72 memory module uses 18
ProMOS 64M x 4 DDR SDRAM. The x72 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
-6
-7
-75
-8
D3
200
(PC400B)
Clock Frequency
166
133
125
Module Speed
143
D0
(PC333) (PC266A) (PC266B) (PC200)
(max.)
Clock Frequency (max.)
200
t
AC
Clock Access Time
6
7
7.5
(PC400A)
8
CAS Latency = 2.5
Clock Cycle Time CAS Latency = 2
7.5
t
CK
Clock Cycle Time CAS Latency = 2.5
Clock Cycle Time CAS Latency = 3
A1
PC1600 (100MHz @ CL2)
t
tRCD parameter
B0
RCD
PC2100B (133MHz @ CL2.5)
tRP (133MHz
B1 t
RP
PC2100Aparameter @ CL2)
C0
PC2700 (166MHz @ CL2.5)
5
5
3
3
C0
166
(PC333)
Units
MHz
ns
ns
ns
CLK
CLK
7.5
6
5
3
3
7.5
6
-
3
3
Module Speed
V827464N24SC Rev. 1.2 April 2006
1
ProMOS TECHNOLOGIES
Part Number Information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V827464N24SC
15
16
17
V
ProMOS
TYPE
8 : DDR
8
2
7 4
6 4
DATA
DEPTH
16 : 16Mb
32 : 32 Mb
64 : 64 Mb
65 : 128 Mb
66 : 256 Mb
N
2
REFRESH
RATE
0: 4K
2: 8K
4
S
C
COMPONENT
REV LEVEL
I
X
PCB TYPE
-
D
3
G : GOLD_LEAD PLATING
W : GOLD_RoHS
L : LOW PROFILE_LEAD PLATING
X : LOW PROFILE_RoHS
VOLTAGE
2 : 2.5V
DATA WIDTH
& COMP DENSITY
65
66
67
68
69
73
74
75
76
77
X64 using 128M
X64 using 256M
X64 using 512M
X64 using 1G
X64 using 2G
X72 using 128M
X72 using 256M
X72 using 512M
X72 using 1G
X72 using 2G
MODULE TYPE
& COMP WIDTH
BANKS
4 : 4 Banks
COMPONENT PKG
LEAD
PLATING
T
S
D
Z
I
J
N
P
GREEN
PACKAGE
DESCRIPTION
TSOP
FBGA
Die-stacked TSOP
Die-stacked FBGA
BASED ON
184PIN DIMM
UNBUFFERED
184PIN DIMM
REGISTERED
200PIN
SO-DIMM
172PIN
Micro-DIMM
X4 X16 X8
I
N
V
J
O
B
K
U
G
M
I/O INTERFACE
S: SSTL_2
SPEED
B0 : PC2100B (133MHz @CL2.5-3-3)
B1 : PC2100A (133MHz @CL2-2-2)
C0 : PC2700 (166MHz @CL2.5-3-3)
D0 : PC3200 (200MHz @CL2.5-3-3)
D3 : PC3200 (200MHz @CL3-3-3)
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
Low Profile Module (1.2 in)
FBGA-Based Low Profile Module (1.125 in)
V437432S24V Rev. 1.0 June 2003
10
This 512MB Registered ECC DDR DIMM is available in four different heights: 1.7", 1.2", 1.125", and 1.0".
Please refer to pages 12 to 15 for the detailed mechanical diagrams of all four PCB heights.
V827464N24SC Rev. 1.2 April 2006
2
ProMOS TECHNOLOGIES
Block Diagram
V827464N24SC
VSS
RS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS9
(DM0)
DQ4
DQ5
DQ6
DQ7
D0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D9
DQS1
DQ8
DQ9
DQ10
DQ11
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS10
(DM1)
DQ12
DQ13
DQ14
DQ15
D1
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D10
DQS2
DQ16
DQ17
DQ18
DQ19
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS11
(DM2)
DQ20
DQ21
DQ22
DQ23
D2
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D11
DQS3
DQ24
DQ25
DQ26
DQ27
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS12
(DM3)
DQ28
DQ29
DQ30
DQ31
D3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D12
DQS4
DQ32
DQ33
DQ34
DQ35
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS13
(DM4)
DQ36
DQ37
DQ38
DQ39
D4
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D13
DQS5
DQ40
DQ41
DQ42
DQ43
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS14
(DM5)
DQ44
DQ45
DQ46
DQ47
D5
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
D14
DQS6
DQ48
DQ49
DQ50
DQ51
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS15
(DM6)
DQ52
DQ53
DQ54
DQ55
D6
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
Serial PD
SCL
WP
A0
A1
SA1
A2
SA2
SDA
D15
DQS7
DQ56
DQ57
DQ58
DQ59
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS16
(DM7)
DQ60
DQ61
DQ62
DQ63
D7
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
SA0
D16
V
DDSPD
V
D D
/V
DDQ
CS
DM
DQS8
CB0
CB1
CB2
CB3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS17
(DM8)
CB4
CB5
CB6
CB7
SPD
D0 - D17
D0 - D17
D8
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D17
VREF
V
SS
D0 - D17
D0 - D17
S0
BA0-BAN
A0-A13
RAS
CAS
CKE0
WE
PCK
PCK
R
E
G
I
S
T
E
R
RS0A
RS0B
RBA0 - RBAn
RA0 - RA12
RRAS
RCAS
RCKE0A
RCKE0B
RWE
RESET
BA0 -BAn : SDRAMs DQ0 - D17
A0 -An : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
V827464N24SC Rev. 1.2 April 2006
3
ProMOS TECHNOLOGIES
Pin Configurations (Front Side/Back Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
Key key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
V827464N24SC
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Notes:
*
These pins are not used in this module.
Pin
Pin Description
Power Supply
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
Pin Names
Pin
CK1, CK1, CK2, CK2
CS0
CKE0
RAS, CAS, WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
V827464N24SC Rev. 1.2 April 2006
4
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D0 (PC3200 @ CL 2.5-3-3)
D3 (PC3200 @ CL 3-3-3 )
C0 (PC2700 @ CL 2.5-3-3)
V827464N24SC
Function Supported
Byte #
0
Hex value
D0
D3
80h
Function described
Defines # of Bytes written into serial memory at module
manufacturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
DDR SDRAM cycle time at CAS Latency =2.5
DDR SDRAM Access time from clock at CL=2.5
DIMM configuration type(Non-parity, Parity, ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address
DDR SDRAM device attributes : Burst lengths supported
DDR SDRAM device attributes : # of banks on each DDR
SDRAM
DDR SDRAM device attributes : CAS Latency supported
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
D0
D3
128bytes
C0
C0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
256bytes
SDRAM DDR
13
11
1 Bank
72 bits
-
SSTL 2.5V
5ns
±0.65ns
5ns
±0.65ns
6ns
±0.70ns
50h
65h
08h
07h
0Dh
0Bh
01h
48h
00h
04h
50h
65h
02h
82h
04h
04h
01h
60h
70h
Non-parity, ECC
7.8us & Self refresh
x4
x4
t
CCD
=1CLK
2,4,8
4 banks
16
17
0Eh
04h
18
19
20
21
2,2.5,3
0CLK
1CLK
Registered address &
control inputs and On-card DLL
+/-0.2V voltage tolerance
5.0ns
±0.65ns
7.5ns
±0.75ns
15ns
6.0ns
±0.70ns
7.5ns
±0.75ns
15ns
7.5ns
±0.70ns
-
-
18ns
0Ch
1Ch
01h
02h
26h
1Ch
22
23
24
25
26
27
DDR SDRAM device attributes : General
DDR SDRAM cycle time at CL =2
DDR SDRAM Access time from clock at CL =2
DDR SDRAM cycle time at CL =1.5
DDR SDRAM Access time from clock at CL =1.5
Minimum row precharge time (=t
RP
)
00h
50h
65h
75h
75h
3Ch
60h
70h
75h
75h
3Ch
75h
70h
00h
00h
48h
V827464N24SC Rev. 1.2 April 2006
5
