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VN4012L-GP014

SMALL SIGNAL, FET

器件类别:分立半导体    晶体管   

厂商名称:Microchip(微芯科技)

厂商官网:https://www.microchip.com

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Microchip(微芯科技)
Reach Compliance Code
compliant
Base Number Matches
1
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Supertex inc.
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C
ISS
and fast switching speeds
Excellent thermal stability
Integral source-drain diode
High input impedance and high gain
VN4012
General Description
Applications
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Ordering Information
Part Number
VN4012L-G
VN4012L-G P002
VN4012L-G P003
VN4012L-G P005
VN4012L-G P013
VN4012L-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Package Option
TO-92
Packing
1000/Bag
Product Summary
BV
DSS
/BV
DGS
400V
R
DS(ON)
(max)
V
GS(TH)
(max)
I
DSS
(min)
12Ω
1.8V
150mA
TO-92
2000/Reel
Pin Configuration
DRAIN
SOURCE
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
GATE
TO-92
Product Marking
YY WW
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Si VN
4012L
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
TO-92
Typical Thermal Resistance
Package
TO-92
Doc.# DSFP-VN4012
B082013
Package may or may not include the following marks: Si or
θ
ja
132
O
C/W
Supertex inc.
www.supertex.com
VN4012
Thermal Characteristics
Package
TO-92
(continuous)
I
D
(pulsed)
I
D
Power Dissipation
@T
C
= 25
O
C
I
DR
160mA
I
DRM
650mA
160mA
650mA
1.0W
Notes:
† I
D
(continuous) is limited by max rated T
j
.
Electrical Characteristics
(T
Sym
BV
DSS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
r
t
d(ON)
t
f
t
d(OFF)
V
SD
Parameter
A
= 25
O
C unless otherwise specified)
Min
400
0.6
-
-
Typ
-
-
-
-
-
0.3
9.5
17
350
-
-
-
-
-
-
-
-
Max
-
1.8
10
1
100
-
12
30
-
110
30
10
20
20
65
65
1.2
Units
V
V
nA
µA
A
Ω
Conditions
V
GS
= 0V, I
D
= 100µA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ±20V, V
DS
= 0V
V
GS
= 0V, V
DS
= 0.8 Max Rating
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125°C
V
GS
= 4.5V, V
DS
= 10V
V
GS
= 4.5V, I
D
= 100mA
V
GS
= 4.5V, I
D
= 100mA, T
A
= 125
O
C
Drain-to-source breakdown voltage
Gate threshold voltage
Gate body leakage
Zero gate voltage drain current
On-state drain current
Static drain-to-source on-state
resistance
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Rise time
Turn-on delay time
Fall time
Turn-off delay time
Diode forward voltage drop
-
0.15
-
-
125
-
-
-
-
-
-
-
-
mmho V
DS
= 15V, I
D
= 100mA
pF
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
ns
V
DD
= 25V,
I
D
= 100mA,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= 160mA
V
Notes:
1. All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
90%
10%
t
(ON)
VDD
Pulse
Generator
R
L
OUTPUT
INPUT
0V
t
(OFF)
t
r
t
d(OFF)
t
f
10%
90%
90%
R
GEN
t
d(ON)
VDD
OUTPUT
0V
10%
INPUT
D.U.T.
Doc.# DSFP-VN4012
B082013
2
Supertex inc.
www.supertex.com
VN4012
3-Lead TO-92 Package Outline (L)
D
A
Seating
Plane
1
2
3
L
b
e1
e
c
Front View
Side View
E1
E
1
2
3
Bottom View
Symbol
Dimensions
(inches)
MIN
NOM
MAX
A
.170
-
.210
b
.014
-
.022
c
.014
-
.022
D
.175
-
.205
E
.125
-
.165
E1
.080
-
.105
e
.095
-
.105
e1
.045
-
.055
L
.500
-
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Supertex inc.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.”
Supertex inc.
does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the
Supertex inc.
(website: http//www.supertex.com)
©2013
Supertex inc.
All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-VN4012
B082013
3
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Supertex inc.
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