W39L040A Data Sheet
512K
×
8 CMOS FLASH MEMORY
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
BLOCK DIAGRAM ...................................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 4
FUNCTIONAL DESCRIPTION ................................................................................................... 5
6.1
Device Bus Operation..................................................................................................... 5
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Read Mode.......................................................................................................................5
Write Mode .......................................................................................................................5
Standby Mode ..................................................................................................................5
Output Disable Mode........................................................................................................5
Auto-select Mode..............................................................................................................5
6.2
Data Protection ............................................................................................................... 6
6.2.1
6.2.2
6.2.3
6.2.4
Low VDD Inhibit................................................................................................................6
Write Pulse "Glitch" Protection .........................................................................................6
Logical Inhibit ...................................................................................................................6
Power-up Write and Read Inhibit......................................................................................6
6.3
Command Definitions ..................................................................................................... 6
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Read Command ...............................................................................................................6
Auto-select Command ......................................................................................................7
Byte Program Command ..................................................................................................7
Chip Erase Command ......................................................................................................7
Sector Erase Command ...................................................................................................8
6.4
Write Operation Status ................................................................................................... 8
6.4.1
6.4.2
DQ7: #Data Polling...........................................................................................................8
DQ6: Toggle Bit................................................................................................................9
6.5
Table of Operating Modes .............................................................................................. 9
6.5.1
6.5.2
6.5.3
6.5.4
Device Bus Operations.....................................................................................................9
Auto-select Codes (High Voltage Method) .......................................................................9
Sector Address Table .....................................................................................................10
Command Definitions .....................................................................................................10
6.6
6.7
Embedded Programming Algorithm ............................................................................. 11
Embedded Erase Algorithm.......................................................................................... 12
Publication Release Date:April 14, 2005
Revision A3
-1-
W39L040A
6.8
6.9
7.
7.1
7.2
7.3
7.4
Embedded #Data Polling Algorithm.............................................................................. 13
Embedded Toggle Bit Algorithm ................................................................................... 13
Absolute Maximum Ratings .......................................................................................... 14
DC Operating Characteristics....................................................................................... 14
Pin Capacitance............................................................................................................ 14
AC Characteristics ........................................................................................................ 15
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
AC Test Conditions.........................................................................................................15
AC Test Load and Waveform .........................................................................................15
Read Cycle Timing Parameters......................................................................................16
Erase/Program Cycle Timing Parameters ......................................................................16
Power-up Timing ............................................................................................................17
#Data Polling and Toggle Bit Timing Parameters ...........................................................17
ELECTRICAL CHARACTERISTICS......................................................................................... 14
8.
TIMING WAVEFORMS ............................................................................................................. 18
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Read Cycle Timing Diagram......................................................................................... 18
#WE Controlled Command Write Cycle Timing Diagram............................................. 18
#CE Controlled Command Write Cycle Timing Diagram.............................................. 19
Chip Erase Timing Diagram ......................................................................................... 19
Sector Erase Timing Diagram ...................................................................................... 20
#Data Polling Timing Diagram ...................................................................................... 20
Toggle Bit Timing Diagram ........................................................................................... 21
9.
10.
11.
ORDERING INFORMATION .................................................................................................... 22
HOW TO READ THE TOP MARKING...................................................................................... 23
PACKAGE DIMENSIONS ......................................................................................................... 24
11.1
11.2
11.3
11.4
32L PLCC ..................................................................................................................... 24
32L PDIP....................................................................................................................... 24
32L TSOP (8 x 20 mm)................................................................................................. 25
32L STSOP (8 x 14 mm) .............................................................................................. 25
12.
VERSION HISTORY ................................................................................................................. 26
-2-
W39L040A
1. GENERAL DESCRIPTION
The W39L040A is a 4Mbit, 3V/3.3V CMOS flash memory organized as 512K
×
8 bits. For flexible
erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The byte-wide (×
8) data appears on DQ7
−
DQ0. The device can be programmed and erased in-system with a
standard 3.3V power supply. A 12-volt V
PP
is not required. The unique cell architecture of the
W39L040A results in fast program/erase operations with extremely low current consumption
(compared to other comparable 3.3-volt flash memory products). The device can also be programmed
and erased by using standard EPROM programmers.
2. FEATURES
•
3V/3.3-Volt Read/Erase/Program Operations
−
3.0 ~ 3.6V for 70nS
−
2.7 ~ 3.6V for 90nS
•
•
•
Typical program/erase cycles: 10K
Twenty-year data retention
Low power consumption
−
Active read current: 7 mA at 5MHz (typ.)
−
Active program/erase current: 15 mA at
5MHz (typ.)
−
Standby current: 0.2
μA
(typ.)
End of program detection
−
Software method: Toggle bit/#Data polling
JEDEC standard byte-wide pinouts
Available packages: 32-pin PLCC Lead free,
32-pin STSOP (8 x 14 mm) Lead free, 32-pin
PDIP and 32-pin TSOP (8 x 20 mm)
•
Fast Program operation:
−
Byte-by-Byte programming: 9
μS
(typ.)
Fast Erase operation:
−
Chip Erase cycle time: 6 S (typ.)
−
Sector Erase cycle time: 0.7 S (typ.)
•
•
•
•
•
•
•
Read access time: 70/90 nS
8 Even sectors with 64K bytes
Any individual sector can be erased
-3-
Publication Release Date: April 14, 2005
Revision A3
W39L040A
3. PIN CONFIGURATIONS
A
1
2
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
A
1
5
3
A
1
6
2
A
1
8
1
V
D
D
#
W
E
A
1
7
4. BLOCK DIAGRAM
32 31 30
29
28
27
26
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
V
DD
V
SS
#CE
#OE
#WE
OUTPUT
BUFFER
DQ0
.
.
32L PLCC
CONTROL
25
24
23
22
21
DQ7
D
Q
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
Q
2
V
D
S
Q
S
3
D
Q
4
D
Q
5
D
Q
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
V SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
A14
A17
#WE
V
DD
A18
A16
A15
A12
A7
A6
A5
A4
.
.
A18
DECODER
CORE
ARRAY
32L STSOP and 32L TSOP
5. PIN DESCRIPTION
SYMBOL
PIN NAME
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
V
DD
#WE
A17
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
A0
−
A18
DQ0
−
DQ7
#CE
#OE
#WE
V
DD
V
SS
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
32-pin
DIP
26
25
24
23
22
21
20
19
18
17
-4-
W39L040A
6. FUNCTIONAL DESCRIPTION
6.1 Device Bus Operation
6.1.1
Read Mode
The read operation of the W39L040A is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high. Refer to the timing waveforms for further details.
6.1.2
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the function
of the device.
The command register itself does not occupy any addressable memory location. The register is a
latch used to store the commands, along with the address and data information needed to execute the
command. The command register is written by bringing #WE to logic low state; while #CE is at logic
low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Program Waveforms for specific timing parameters.
6.1.3
Standby Mode
The Standby mode is achieved with the
#CE input held at V
DD
±0.3V
and the current is typically reduced to
less than 5μA (max).
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
6.1.4
Output Disable Mode
With the #OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
6.1.5
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended for use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5V to 12.5V) on address pin
A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from
V
IL
to V
IH
. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes").
The manufacturer and device codes may also be read via the command register, for instance, when
the W39L040A is erased or programmed in a system without access to high voltage on the A9 pin.
The command sequence is illustrated in "Auto-select Codes".
-5-
Publication Release Date: April 14, 2005
Revision A3
模拟与混合信号
