White Electronic
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY*
1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: V
CC
= 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
• Consult factory for availability of lead-free
products.
DESCRIPTION
The W3EG72126S is a 128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 128Mx4
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SYMBOL
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
CC
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
CCQ
NC
NC
V
SS
DQ10
DQ11
CKE0
V
CCQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
CCQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
CC
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
CC
PIN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
CCQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
CCQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
V
CC
NC
DQ48
DQ49
V
SS
NC
NC
V
CCQ
DQS6
DQ50
DQ51
V
SS
V
CCID
DQ56
DQ57
V
CC
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
SYMBOL
V
SS
DQ4
DQ5
V
CCQ
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
CCQ
DQ12
DQ13
DQS10
V
CC
DQ14
DQ15
NC
V
CCQ
NC
DQ20
A12
V
SS
DQ21
A11
DQS11
V
CC
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
CCQ
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
CCQ
CK0
CK0#
PIN
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
SYMBOL
V
SS
DQS17
A10
CB6
V
CCQ
CB7
V
SS
DQ36
DQ37
V
CC
DQS13
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
CCQ
CS0#
NC
DQS14
V
SS
DQ46
DQ47
NC
V
CCQ
DQ52
DQ53
NC
V
CC
DQS15
DQ54
DQ55
V
CCQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
CCQ
SA0
SA1
SA2
V
CCSPD
A0-A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17
CK0
CK0#
CKE0
CS0#
RAS#
CAS#
WE#
V
CC
V
CCQ
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
RESET#
PIN NAMES
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
V
CC
Indentification Flag
No Connect
Reset Enable
November 2004
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
FUNCTIONAL BLOCK DIAGRAM
V
SS
RCS0#
DQS0
DQ0
DQ1
DQ2
DQ3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ4
DQ5
DQ6
DQ7
CS#
DM
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
DQS9
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS1
DQ8
DQ9
DQ10
DQ11
DQS10
DQ12
DQ13
DQ14
DQ15
CS#
DM
DQS2
CS#
DM
DQS11
CS#
DM
DQS3
DQ16
DQ17
DQ18
DQ19
CS#
DM
DQS12
DQ20
DQ21
DQ22
DQ23
CS#
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS#
DM
CKO
PLL
CS#
DM
SDRAM
DQS4
DQ32
DQ33
DQ34
DQ35
DQS13
DQ36
DQ37
DQ38
DQ39
CKO#
REGISTER
DQS5
CS#
DM
DQS14
CS#
DM
DQS6
DQ40
DQ41
DQ42
DQ43
CS#
DM
DQS15
DQ44
DQ45
DQ46
DQ47
Serial PD
SCL
WP
SDA
A0
A1
A2
SA2
SA0 SA1
CS#
DM
DQ48
DQ49
DQ50
DQ51
DQS7
DQ56
DQ57
DQ58
DQ59
DQS16
CS#
DM
DQ52
DQ53
DQ54
DQ55
CS#
DM
DQ60
DQ61
DQ62
DQ63
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DQS8
DQS17
CS#
DM
CB4
CB5
CB6
CB7
CS#
DM
CB0
CB1
CB2
CB3
CS0#
BA0-BA1
RAS#
A0-A12
CAS#
CKE0
WE#
PCK
PCK#
R
E
G
I
S
T
E
R
RCS0#
RBA0 - RBA1
RA0 - RA12
RRAS#
RCAS#
RCKE0
RWE#
RESET#
BA0 - BA1: DDR SDRAMs
A0 - A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
WE: DDR SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specified
Notes:
1.
DQ-to-I/O wiring is shown as recommended but may be changed.
2.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
November 2004
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
27
50
Units
V
V
°C
W
mA
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
T
A
70°C, V
CC
= 2.5V ± 0.2V
Min
2.3
2.3
1.15
1.15
V
REF
+ 0.15
-0.3
V
TT
+ 0.76
—
Max
2.7
2.7
1.35
1.35
V
CCQ
+ 0.3
V
REF
-0.15
—
V
TT
-0.76
Unit
V
V
V
V
V
V
V
V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
CAPACITANCE
T
A
= 25°C. f = 1MHz, V
CC
= 2.5V ± 0.2V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
C
OUT
Max
6.25
6.25
6.25
5.5
6.25
8
6.25
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
November 2004
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
T
A
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM component only
DDR333@CL=2.5
Max
2340
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
RC
=t
RC
(MIN);
t
CK
=t
CK
(MIN); l
OUT
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
CS# = High; All device banks idle;
t
CK
=t
CK
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
CK
=t
CK
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
t
RC
= t
RC
(MIN)
CKE
0.2V
DDR266@CL=2, 2.5
Max
2340
DDR200@CL=2
Max
2340
Units
mA
Operating Current
I
DD1
2880
2880
2880
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
I
DD2F
90
810
90
810
90
810
rnA
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
I
DD3N
630
900
630
900
630
900
mA
mA
Operating Current
I
DD4R
2970
2970
2970
mA
Operating Current
I
DD4W
3150
2790
2790
rnA
Auto Refresh
Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
5220
90
7290
5220
90
7200
5220
90
7200
mA
mA
mA
Four bank interleaving Reads (BL=4)
with auto precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and
control inputs change only during
Active Read or Write commands.
November 2004
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
