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W3EG7218S262AD4

128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL

器件类别:存储    存储   

厂商名称:White Electronic Designs Corporation

厂商官网:http://www.wedc.com/

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
White Electronic Designs Corporation
包装说明
DIMM,
Reach Compliance Code
unknow
访问模式
FOUR BANK PAGE BURST
最长访问时间
0.75 ns
其他特性
AUTO/SELF REFRESH
JESD-30 代码
R-XDMA-N200
内存密度
1207959552 bi
内存集成电路类型
DDR DRAM MODULE
内存宽度
72
功能数量
1
端口数量
1
端子数量
200
字数
16777216 words
字数代码
16000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
16MX72
封装主体材料
UNSPECIFIED
封装代码
DIMM
封装形状
RECTANGULAR
封装形式
MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
自我刷新
YES
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子形式
NO LEAD
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
文档预览
White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL
FEATURES
Double-data-rate architecture
DDR200 and DDR266
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
Package height options:
AD4: 35.5mm (1.38") and
BD4: 31.75mm (1.25")
* This product is under development, is not qualified or characterized and is subject to
change without notice.
DESCRIPTION
The W3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of nine
16Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
OPERATING FREQUENCIES
DDR266 @CL=2
Clock Speed
CL-t
RCD
-t
RP
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
V
REF
V
REF
V
SS
V
SS
DQ0
DQ4
DQ1
DQ5
V
CC
V
CC
DQS0
DQM0
DQ2
DQ6
V
SS
V
SS
DQ3
DQ7
DQ8
DQ12
V
CC
V
CC
DQ9
DQ13
DQS1
DQM1
V
SS
V
SS
DQ10
DQ14
DQ11
DQ15
V
CC
V
CC
CK0
V
CC
CK0#
V
SS
V
SS
V
SS
DQ16
DQ20
DQ17
DQ21
V
CC
V
CC
DQS2
DQM2
DQ18
DQ22
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
V
SS
V
SS
DQ19
DQ23
DQ24
DQ28
V
CC
V
CC
DQ25
DQ29
DQS3
DQM3
V
SS
V
SS
DQ26
DQ30
DQ27
DQ31
V
CC
V
CC
CB0
CB4
CB1
CB5
V
SS
V
SS
DQS8
DQM8
CB2
CB6
V
CC
V
CC
CB3
CB7
NC
NC
V
SS
V
SS
NC
V
SS
NC
V
CC
V
CC
V
CC
NC
CKE0
NC
NC
NC
A11
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
AB
V
SS
V
SS
A7
A6
A5
A4
A3
A2
A1
A0
V
CC
V
CC
A10/AP
BA1
RA0
RAS#
WE#
CAS#
CS0
NC
NC
NC
V
SS
V
SS
DQ32
DQ36
DQ33
DQ37
V
CC
V
CC
DQS4
DQM4
DQ34
DQ38
V
SS
V
SS
DQ35
DQ39
DQ40
DQ44
V
CC
V
CC
DQ41
DQ45
DQS5
DQM5
V
SS
V
SS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
NC
V
SS
NC
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DQM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DQM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
V
CCID
NC
A0-A11
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
CK0#
CKE0
CS0#
RAS#
CAS#
WE#
V
CC
V
CCQ
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
V
CCID
NC
W3EG7218S-AD4
-BD4
PRELIMINARY
PIN NAMES
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply (2.5V)
Power Supply for DQS (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial Data I/O
Serial Clock
Address in EEPROM
V
CC
Identification Flag
No Connect
DQM0-DQM8 Data-In Mask
November 2004
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DQM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK0
CK0#
120
PLL
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS7
DQM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6
DQM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS4
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
W3EG7218S-AD4
-BD4
PRELIMINARY
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 2
DDR SDRAM X 1
SERIAL PD
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
V
DDSPD
V
DD
V
REF
V
SS
SPD/EEPROM
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
WE#
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
WE#
Note: All resistor values are 22Ω unless otherwise indicated
November 2004
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG7218S-AD4
-BD4
PRELIMINARY
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
Value
– 0.5 ~ 3.6
–1.0 ~ 3.6
– 55 ~ +150
9
50
Units
V
V
°C
W
mA
0°C
T
A
70°C,
V
CC
= 2.5V ± 0.2V
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
Min
2.3
2.3
1.15
1.15
V
REF
+ 0.15
– 0.3
V
TT
+ 0.76
Max
2.7
2.7
1.35
1.35
V
CCQ
+ 0.3
V
REF
– 0.15
V
TT
– 0.76
Unit
V
V
V
V
V
V
V
V
DC CHARACTERISTICS
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 2.5V
Parameter
Input Capacitance (A0-A11)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#,CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output Capacitance (DQ0-DQ63)(DQS)
Data input/output Capacitance (CB0-CB7)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
C
OUT
Max
29
29
29
5.5
29
8
29
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
November 2004
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
I
DD
SPECIFICATIONS AND TEST CONDITIONS
DDR266
@CL=2
Parameter
Operating Current
Symbol Conditions
I
DD0
One device bank; Active - Precharge; (MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address and control
inputs changing once every two cycles. t
RC
=t
RC
(MIN); t
CK
=t
CK
One device bank; Active-Read-Precharge; Burst = 2;
t
RC
=t
RC
(MIN);t
CK
=t
CK
(MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
All device banks idle; Power-down mode; t
CK
=t
CK
(MIN);
CKE=(low)
CS# = High; All device banks idle; t
CK
=t
CK
(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
V
IN
= V
REF
for DQ, DQS and DM.
One device bank active; Power-down mode; t
CK
(MIN);
CKE=(low)
CS# = High; CKE = High; One device bank; Active-Precharge;
t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; t
CK
=t
CK
(MIN); I
OUT
= 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
t
CK
=t
CK
(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
t
RC
=t
RC
(MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto precharge with
t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); Address and control inputs change
only during Active Read or Write commands
Max
1125
W3EG7218S-AD4
-BD4
PRELIMINARY
(Recommended operating conditions, 0°C
T
A
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V)
DDR266
@CL=2.5
Max
990
DDR200
@CL=2
Max
990
Units
mA
Operating Current
I
DD1
1215
1080
1080
mA
Precharge Power-
Down Standby Current
Idle Standby Current
I
DD2P
I
DD2F
27
405
27
405
27
405
mA
mA
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
I
DD3N
225
450
225
450
225
450
mA
mA
Operating Current
I
DD4R
1260
1170
1170
mA
Operating Current
I
DD4W
1260
1125
1125
mA
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
2385
27
3195
1980
27
2970
1980
27
2970
mA
mA
mA
November 2004
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
查看更多>
参数对比
与W3EG7218S262AD4相近的元器件有:W3EG7218S-AD4、W3EG7218S202BD4、W3EG7218S262BD4、W3EG7218S265BD4、W3EG7218S-BD4、W3EG7218S202AD4。描述及对比如下:
型号 W3EG7218S262AD4 W3EG7218S-AD4 W3EG7218S202BD4 W3EG7218S262BD4 W3EG7218S265BD4 W3EG7218S-BD4 W3EG7218S202AD4
描述 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL 128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL
是否Rohs认证 不符合 - 不符合 不符合 不符合 - 不符合
厂商名称 White Electronic Designs Corporation - White Electronic Designs Corporation White Electronic Designs Corporation White Electronic Designs Corporation - White Electronic Designs Corporation
包装说明 DIMM, - DIMM, DIMM, DIMM, - DIMM,
Reach Compliance Code unknow - unknow unknow unknow - unknow
访问模式 FOUR BANK PAGE BURST - FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST - FOUR BANK PAGE BURST
最长访问时间 0.75 ns - 0.75 ns 0.75 ns 0.75 ns - 0.75 ns
其他特性 AUTO/SELF REFRESH - AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH - AUTO/SELF REFRESH
JESD-30 代码 R-XDMA-N200 - R-XDMA-N200 R-XDMA-N200 R-XDMA-N200 - R-XDMA-N200
内存密度 1207959552 bi - 1207959552 bi 1207959552 bi 1207959552 bi - 1207959552 bi
内存集成电路类型 DDR DRAM MODULE - DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE - DDR DRAM MODULE
内存宽度 72 - 72 72 72 - 72
功能数量 1 - 1 1 1 - 1
端口数量 1 - 1 1 1 - 1
端子数量 200 - 200 200 200 - 200
字数 16777216 words - 16777216 words 16777216 words 16777216 words - 16777216 words
字数代码 16000000 - 16000000 16000000 16000000 - 16000000
工作模式 SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS - SYNCHRONOUS
最高工作温度 70 °C - 70 °C 70 °C 70 °C - 70 °C
组织 16MX72 - 16MX72 16MX72 16MX72 - 16MX72
封装主体材料 UNSPECIFIED - UNSPECIFIED UNSPECIFIED UNSPECIFIED - UNSPECIFIED
封装代码 DIMM - DIMM DIMM DIMM - DIMM
封装形状 RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR
封装形式 MICROELECTRONIC ASSEMBLY - MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY - MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified - Not Qualified
自我刷新 YES - YES YES YES - YES
最大供电电压 (Vsup) 2.7 V - 2.7 V 2.7 V 2.7 V - 2.7 V
最小供电电压 (Vsup) 2.3 V - 2.3 V 2.3 V 2.3 V - 2.3 V
标称供电电压 (Vsup) 2.5 V - 2.5 V 2.5 V 2.5 V - 2.5 V
表面贴装 NO - NO NO NO - NO
技术 CMOS - CMOS CMOS CMOS - CMOS
温度等级 COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL - COMMERCIAL
端子形式 NO LEAD - NO LEAD NO LEAD NO LEAD - NO LEAD
端子位置 DUAL - DUAL DUAL DUAL - DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
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