1GB – 128M x 72 DDR2 SDRAM
208 PBGA Multi-Chip Package
W3H128M72E-XSBX / W3H128M72E-XNBX
FEATURES
Data rate = 667, 533, 400
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
• 1.0mm pitch
Core Supply Voltage = 1.8V
I/O Supply Voltage = 1.8V - (SSTL_18 compatible)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with clock
signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
CK/CK# Termination options available
• 0 ohm, 20 ohm
Write latency = Read latency - 1* t
CK
Commercial, Industrial and Military Temperature Ranges
Organized as 128M x 72
Weight: W3H128M72E-XSBX - 4 grams max
Weight: W3H128M72E-XNBX - TBD
BENEFITS
56% space savings vs. FBGA
Reduced part count
50% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
* This product is subject to change without notice.
TYPICAL APPLICATION
RAM
Host
FPGA/
Processor
DDR2 / DDR3
W3H128M72E-XSBX / -XNBX
SSD (SLC)
MSM032 / MSM064 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
5in
)
n
MSD1TB / 512 / 256 / 128 (SATA, 2.5in)
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
11.5
11.5
11.5
11.5
11.5
22
14.0
84
FBGA
84
FBGA
84
FBGA
84
FBGA
84
FBGA
W3H128M72E-XXXX
W3H128M72E-XXXX
16
S
A
V
I
N
G
S
56%
50%
Area
I/O Count
5 x 161mm
2
= 805mm
2
5 x 84 balls = 420 balls
352mm
2
208 Balls
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4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS#
WE#
RAS#
CAS#
CKE
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
DQ0
¥
CK
CK#
LDM
UDM
LDQS
LDQS#
UDQS
UDQS#
ODT
A0-13
BA0-2
CK0
CK0#
LDM0
UDM0
LDQS0
LDQS0#
UDQS0
UDQS0#
DQ0
U0
¥
¥
¥
¥
¥
DQ15
¥
¥
¥
¥
¥
¥
DQ15
CK1
CK1#
LDM1
UDM1
LDQS1
LDQS1#
UDQS1
UDQS1#
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
BA0-2
¥
CK
CK#
LDM
UDM
LDQS
LDQS#
UDQS
UDQS#
DQ16
U1
¥
¥
¥
¥
¥
DQ15
¥
¥
¥
¥
¥
¥
DQ31
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
CK2
CK2#
LDM2
UDM2
LDQS2
LDQS2#
UDQS2
UDQS2#
CK
CK#
LDM
UDM
LDQS
LDQS#
UDQS
UDQS#
DQ0
DQ32
U2
¥
¥
¥
¥
¥
¥
DQ15
¥
¥
¥
¥
¥
¥
DQ47
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
BA0-2
CK3
CK3#
LDM3
UDM3
LDQS3
LDQS3#
UDQS3
UDQS3#
CK
CK#
LDM
UDM
LDQS
LDQS#
UDQS
UDQS#
DQ48
U3
¥
¥
¥
¥
¥
¥
DQ15
¥
¥
¥
¥
¥
¥
DQ63
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
BA0-2
CK4
CK4#
LDM4
V
CC
LDQS4
LDQS4#
UDQS4
UDQS4#
CK
CK#
LDM
UDM
LDQS
LDQS#
UDQS
UDQS#
DQ64
U4
¥
¥
¥
¥
¥
¥
DQ7
¥
¥
¥
¥
¥
¥
DQ71
NOTE: Connect UDQS4 to ground via a resistor and UDQS4#
to V
CC
via a resistor. UDM4 is internally tied to V
CC
.
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W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CC
2
V
CC
3
V
SS
4
V
CC
5
V
CC
6
V
SS
7
V
CC
8
V
CC
9
V
SS
10 11
V
CC
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
SS
NC
NC
NC
NC
NC
NC
NC
V
SS
V
CC
V
SS
NC
NC
NC
NC
NC
NC
DQ34
CK3
CK3#
V
SS
DQ35
DQ51
NC
NC
NC
NC
DQ50
DQ53
DQ37
CK2#
CK2
DQ52
DQ36
DQ33
NC
BA2
DNU
DQ39
LDQS2
LDQS3
DQ48
DQ32
LDM3
LDM2
DQ49
DQ43
DQ59
DNU
DQ55
DQ58
DQ42
LDQS2#
LDQS3#
DQ38
DQ54
DQ60
DQ57
UDM2
V
SS
DQ63
DQ56
DQ40
DQ61
DQ45
UDM3
DQ44
DQ41
DQ46
DQ62
V
CC
UDQS2#
DQ47
UDQS2
UDQS3
UDQS3#
V
CC
A6
A10
A9
V
CC
V
SS
V
CC
A3
A12
A13
V
CC
V
SS
A0
A11
V
CC
V
SS
V
REF
V
SS
V
CC
A1
BA1
V
SS
V
CC
A2
A4
A8
V
CC
V
SS
V
CC
BA0
A5
A7
V
CC
UDQS1#
UDQS1
UDQS0
DQ15
UDQS0#
V
CC
DQ30
DQ14
DQ9
DQ12
UDM1
DQ13
DQ29
DQ8
DQ24
DQ31
V
SS
UDM0
DQ25
DQ28
DQ22
DQ6
LDQS1#
LDQS0#
DQ10
DQ26
DQ23
ODT
DQ27
DQ11
DQ17
LDM0
LDM1
DQ0
DQ16
LDQS1
LDQS0
DQ7
LDQS4#
UDQS4
UDQS4#
DQ1
DQ4
DQ20
CK0
CK0#
DQ5
DQ21
DQ18
LDQS4
DQ71
CKE
WE#
DQ19
DQ3
V
SS
CK1#
CK1
DQ2
RAS#
CAS#
DQ64
DQ70
DQ65
DQ68
V
SS
V
CC
V
SS
CK4#
CK4
CS#
DQ66
DQ69
LDM4
DQ67
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
V
CC
V
SS
Vcc
V
CC
V
SS
V
CC
V
SS
1
2
3
4
5
6
7
8
9
10 11
NOTE: Connect UDQS4 to ground via a resistor and UDQS4# to V
CC
via a resistor.
UDM4 is internally tied to V
CC
Balls F6 and E6 are reserved for A14 and A15 on future densities.
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4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
W3H128M72E-XSBX / W3H128M72E-XNBX
TABLE 1 – BALL DESCRIPTIONS
Symbol
ODT
CK, CK#
Type
Input
Input
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if
disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE
is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V
CC
is applied during
fi
rst power-up. After V
REF
has
become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, V
REF
must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when
CS# is registered HIGH.
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4
Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–
BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10
HIGH) The address inputs also provide the op-code during a LOAD MODE command.
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
Power Supply: I/O + core, V
CCQ
is common to V
CC
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
CKE
Input
CS#
RAS#, CAS#, WE#
LDM, UDM
BA0–BA2
Input
Input
Input
Input
A0-A13
Input
DQ0-71
UDQS, UDQS#
I/O
I/O
LDQS, LDQS#
V
CC
V
REF
V
SS
NC
DNU
I/O
Supply
Supply
Supply
-
-
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4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
W3H128M72E-XSBX / W3H128M72E-XNBX
DESCRIPTION
The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-
access memory containing
fi
ve 2Gb 2,147,483,648 bits chips. Each
of the
fi
ve chips in the MCP are internally configured as 8-bank
DRAM. The block diagram of the device is shown in Figure 2. Ball
assignments are shown in Figure 3.
The 8Gb DDR2 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 4n-prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 8Gb DDR2 SDRAM effectively consists
of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding
n-bit-wide,
one-half-clock-cycle
data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM during READs and by the
memory controller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs. Two strobes
per chip, one for the lower byte (LDQS, LDQS#) and one for the
upper byte (UDQS, UDQS#).
The 8Gb DDR2 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write
burst lengths of four or eight locations. DDR2 SDRAM supports
interrupting a burst read of eight with another read, or a burst
write of eight with another write. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
A self refresh mode is provided, along with a power-saving power-
down mode.
All inputs are compatible with the JEDEC standard for SSTL_18.
All full drive-strength outputs are SSTL_18-compatible.
GENERAL NOTES
The functionality and the timing specifications discussed in this
data sheet are for the DLL-enabled mode of operation.
Throughout the data sheet, the various
fi
gures and text refer to
DQs as “DQ.” The DQ term is to be interpreted as any and all
DQ collectively, unless specifically stated otherwise. Additionally,
each chip is divided into 2 bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS
refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to
UDM and DQS refers to UDQS. Note that the there is no upper
byte for U4 and therefore no UDM4.
Complete functionality is described throughout the document
and any page or diagram may have been simplified to convey a
topic and may not be inclusive of all requirements.
Any specific requirement takes precedence over a general
statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. The following
sequence is required for power up and initialization and is
shown in Figure 4 on page 6.
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