Preliminary W9321
ADPCM CODEC
Table of Contents-
1. GENERAL DESCRIPTION ...........................................................................................................................2
2. FEATURES ..................................................................................................................................................2
3. PIN CONFIGURATION.................................................................................................................................3
4. PIN DESCRIPTIONS ....................................................................................................................................3
4.1. Power Control Interface.......................................................................................................................3
4.2. Analog Interface ..................................................................................................................................4
4.3. ADPCM/PCM Serial Interface ..............................................................................................................5
4.4. Serial Setup Port(SSP) Interface .........................................................................................................5
5. SYSTEM DIAGRAM.....................................................................................................................................6
5.1 Pair Gain System .................................................................................................................................6
5.2. Cordless Phone System ......................................................................................................................7
6. BLOCK DIAGRAM.......................................................................................................................................8
7. FUNCTIONAL DESCRIPTIONS ...................................................................................................................8
7.1. Power Supply Management System ....................................................................................................8
7.2.
7.3.
7.4.
7.5.
7.6.
Σ∆
Codec-Filter ...................................................................................................................................9
DSP Engine ........................................................................................................................................9
Serial Setup Port (SSP).....................................................................................................................12
Sequence and Control .......................................................................................................................14
I/O Level ...........................................................................................................................................14
8. CONTROL AND STATUS REGISTERS......................................................................................................14
8.1. Introduction.......................................................................................................................................15
8.2. Byte Register Description ..................................................................................................................15
9. ELECTRICAL CHARACTERISTICS ...........................................................................................................24
9.1. Absolute Maximum Ratings...............................................................................................................24
9.2. DC Characteristics ............................................................................................................................24
9.3. Analog Transmission Characteristics.................................................................................................25
9.4. Analog Electrical Characteristics .......................................................................................................26
9.5. Digital Switching Characteristics........................................................................................................27
10. APPLICATION INFORMATION................................................................................................................30
10.1. Handset Application for Wireless Communication............................................................................30
10.2. Transformer Application for Public Switching Telephone Network (PSTN)........................................30
11. HOW TO PROGRAM THE TONE GENERATOR ......................................................................................31
11.1. Introduction .....................................................................................................................................31
11.2. Tone Frequency Coefficient Calculation...........................................................................................32
11.3. Tone Attenuation Coefficient Calculation .........................................................................................32
11.4. Frequency Coefficients for the DTMF Signal ....................................................................................32
12. PACKAGE DIMENSIONS ........................................................................................................................33
-1-
Publication Release Date: May 1999
Revision A1
Preliminary W9321
1. GENERAL DESCRIPTION
The Winbond ADPCM Codec is a single channel chip incorporating a
Σ∆
PCM codec filter with a 32K,
24K, 16K ADPCM encoder/decoder complying with the CCITT G.721 and G.726 standards. In
addition, this chip also meets the PCM conformance specification of the CCITT G.714
recommendation.
This chip allows full-duplex operation over a wide voltage range from 2.7 to 5.25 volts; it's low power
consumption makes it ideal for battery or AC powered applications. The chip includes a serial setup
port (SSP) interface with a 16 byte setup and status registers. A microcontroller can access many
built-in features through the SSP interface. In addition, this chip also consists of some OP amplifiers
integrated with a
Σ∆
PCM codec-filter to allow for easy control of the analog interface.
This chip can be used on two key applications. One application is for wireless telephone systems such
as CT2, DECT. Another application is for public switch telephone network (PSTN) applications such
as pair gain. See the section on application information for more details.
2. FEATURES
•
Single 2.7 to 5.25 volt power supply
•
Master clock rate: 10.24 MHz oscillator typically for Winbond cordless system
•
Typical power consumption of 85 mW for 3 volt; power down of 0.2 mW
•
Full-duplex single channel speech codec
•
Linear 14 bit
Σ∆
PCM codec-filter for A/D and D/A converter
•
Complete Mu-Law and A-Law companding
•
ADPCM transcoder for 64, 32, 24, and 16 Kbps bit rates
•
Serial PCM/ADPCM transfer data rate from 128 to 2048 Kbps
•
Universal programmable dual tone generator such as DTMF application
•
Noise burst detection algorithm for ADPCM receive path
•
Analog input: differential OP amplifier with external gain adjustment for microphone interface
•
Programmable transmit gain, receive attenuation, and sidetone gain
•
Analog output:
−
Differential power driver with 300
Ω
load and external gain adjustment
−
Differential auxiliary driver with 300
Ω
load for ringer interface
•
3 Volt regulator for digital circuit
•
5 Volt charge pump for analog circuit low voltage applications
•
16 Setup and status registers with 8 bits for monitoring microcontroller applications
•
Packaged in 28-pin DIP/SOP
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Preliminary W9321
3. PIN CONFIGURATION
TG
TI-
TI+
VAG
RO
AXO-
AXO+
V
DSP
V
EXT
PI
PO-
PO+
PDI/RESET
SSP En
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
FSR
BCLKR
DR
C1+
C1-
V
SS
MCLK
DT
BCLKT
FST
SSP Rx
SSP Tx
SSP CLK
Figure 3-1
4. PIN DESCRIPTIONS
4.1. Power Control Interface
PIN NAME
V
EXT
V
DSP
PIN NO.
9
8
I/O
I
O
FUNCTION
This pin is the external power supply between 2.7 and 5.25 volt.
This pin should be decoupled to V
SS
with a 0.1
µF
capacitor.
This is the output of the on-chip 3 volt regulator which supplies the
digital circuit of the chip. This pin should be decoupled to V
SS
with
a 0.1
µF
ceramic capacitor. This pin cannot be used for powering
external loads.
This is the output of the on-chip 5 volt charge pump which supplies
the analog circuit. When V
EXT
= +5V
±5%,
V
DD
is an input and
should be connected to V
EXT
externally. Charge pump capacitor
C1+ and C1- should not be used and BR0[b2] must be written into
logic "1". In this case V
EXT
and V
DD
can share the same 0.1
µF
decoupling capacitor to V
SS
. When V
EXT
= 2.7 to 5.25 volt, V
DD
is
a 5 volt charge pump output and should not be connected to V
EXT
.
V
DD
should be decoupled to V
SS
with a 0.1
µF
capacitor. This pin
cannot be used for powering external loads.
This pin connects the analog and digital ground and is typically
connected to 0 volt.
V
DD
28
I/O
V
SS
22
I
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Publication Release Date: May 1999
Revision A1
Preliminary W9321
4.1. Power Control Interface, continued
PIN NAME
VAG
PIN NO.
4
I/O
O
FUNCTION
This is the analog ground output pin which supplies a 2.5 volt
reference voltage for all analog signal processing. This pin should
be decoupled to V
SS
with 0.1
µF
capacitor. This pin becomes high
impedance when the chip enters an analog power down mode.
The charge pump capacitor pins. When V
EXT
= +5V
±5%,
these
capacitors C1+ and C1- should not be used and BR0[b2] must be
written into logic "1". When V
EXT
= 2.7 to 5.25 volt, a 0.1
µF
capacitor should be placed between C1+ and C1-.
The power down/reset input pin. When at logic 0, the chip enters a
power down mode. When it switches from logic 0 to logic 1, this
chip is active and resets the ADPCM transcoder and all circuits.
C1+, C1-
23, 24
I
PDI/RESET
13
I
4.2. Analog Interface
PIN NAME
TG
PIN NO.
1
I/O
O
FUNCTION
This pin is the analog output of the transmit input amplifier. It can
be used to set the gain by external resistors. When the chip is in
analog power down mode, this pin is high impedance.
This pin is the inverting input of the transmit input amplifier.
Connecting this pin and TI+ (pin-3) to V
DD
will force TG into a
high impedance state.
The non-inverting input of the transmit input amplifier. Connecting
this pin and TI- (pin-2) to V
DD
will force TG to be high impedance.
Note this pin may be connected to the VAG pin for an inverting
configuration if the input signal is referenced to the VAG pin.
This pin is the non-inverting analog output of the receive
smoothing filter. This pin can typically drive a 2 KΩ load to 1.13
volt peak referenced to the VAG pin. This pin may be dc
referenced to either the VAG pin or V
EXT
/2 determined by BR2
(b7). When the chip is in analog power down mode, this pin is
high impedance.
This pin is the auxiliary inverting analog output. This pin can drive
a 300
Ω
load differentially. Its output can swing between 0.5 volt
and V
EXT
. This pin may be dc referenced to either the VAG pin or
V
EXT
/2 by BR2 (b7). When the chip is in analog power down
mode, this pin is high impedance.
This pin is the auxiliary non-inverting analog output. This pin can
drive a 300
Ω
load differentially. Its output can swing between 0.5
volt and V
EXT
. This pin may be dc referenced to either the VAG
pin or V
EXT
/2 by BR2 (b7). When the chip is in analog power down
mode, this pin is high impedance.
TI-
2
I
TI+
3
I
RO
5
O
AXO-
6
O
AXO+
7
O
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Preliminary W9321
4.2. Analog Interface, continued
PIN NAME
PI
PIN NO.
10
I/O
I
FUNCTION
This pin is the inverting input to the PO- (pin-11) power amplifier. It
may be dc referenced to either the VAG pin or V
EXT
/2 by BR2 (b7).
This pin and PO- are used to set the gain by using external
resistors. Connecting this pin to V
DD
will power down the chip and
the PO+ and PO- outputs will be high impedance.
This pin is the inverting power amplifier output. Its operation is
same as the AXO- (pin-6). In the application, this pin can drive the
speaker on the receiver.
This pin is the non-inverting power amplifier output. Its operation is
the same as the AXO+ (pin-7). In the application, this pin can drive
the speaker of the receiver.
PO-
11
O
PO+
12
O
4.3. ADPCM/PCM Serial Interface
PIN NAME
MCLK
PIN NO.
21
I/O
I
FUNCTION
This pin is the system master clock input pin. It typically accepts
10.24 MHz for Winbond cordless applications. This pin is the
oscillator input.
This pin is an 8 KHz pulse train for transmission of frame syncs.
This pin synchronizes the output of the DT pin (pin-20).
The bit clock for transmission. It shifts out the data on the DT pin
on the rising edge. The frequency may vary from 128K to 2048
KHz.
This pin is tri-state output data for transmission controlled by FST
and BCLKT pin.
This pin is an 8K Hz pulse train to receive frame syncs. This pin
synchronizes the input of the DR pin (pin-25).
This pin is the receive bit clock. It shifts data on the DR pin into the
chip on the falling edge. The frequency varies from 128K to 2048
KHz.
This pin is the receive input data controlled by the FSR and BCLKR
pins.
FST
BCLKT
18
19
I
I
DT
FSR
BCLKR
20
27
26
O
I
I
DR
25
I
4.4. Serial Setup Port(SSP) Interface
PIN NAME
SSP EN
PIN NO.
14
I/O
I
FUNCTION
This pin is the enable signal for SSP setup. This pin is held low to
select the16 control and status registers. There are two timing
controls. One is for double 8 bit transfer mode; the other control is
for the single 16 bit transfer mode. See the timing diagram, Figure
7-6 to 7-9, in Section 7.4.
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Publication Release Date: May 1999
Revision A1
