W9412G6JH
2M
4 BANKS
16 BITS DDR SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 4
KEY PARAMETERS ................................................................................................................... 5
PIN CONFIGURATION ............................................................................................................... 6
PIN DESCRIPTION ..................................................................................................................... 7
BLOCK DIAGRAM ...................................................................................................................... 8
FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1
7.2
Power Up Sequence ....................................................................................................... 9
Command Function ...................................................................................................... 10
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bank Activate Command ........................................................................... 10
Bank Precharge Command........................................................................ 10
Precharge All Command ............................................................................ 10
Write Command ......................................................................................... 10
Write with Auto-precharge Command ........................................................ 10
Read Command ......................................................................................... 10
Read with Auto-precharge Command ....................................................... 10
Mode Register Set Command.................................................................... 11
Extended Mode Register Set Command ................................................... 11
No-Operation Command ............................................................................ 11
Burst Read Stop Command ....................................................................... 11
Device Deselect Command ....................................................................... 11
Auto Refresh Command ............................................................................ 11
Self Refresh Entry Command .................................................................... 12
Self Refresh Exit Command....................................................................... 12
Data Write Enable /Disable Command ...................................................... 12
Read Operation............................................................................................................. 12
Write Operation ............................................................................................................. 13
Precharge ..................................................................................................................... 13
Burst Termination ......................................................................................................... 13
Refresh Operation ........................................................................................................ 13
Power Down Mode ....................................................................................................... 14
Input Clock Frequency Change during Precharge Power Down Mode ........................ 14
Mode Register Operation .............................................................................................. 14
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Publication Release Date: Nov. 29, 2011
Revision A03
W9412G6JH
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
7.10.6
7.10.7
8.
Burst Length field (A2 to A0) ...................................................................... 14
Addressing Mode Select (A3) .................................................................... 15
CAS Latency field (A6 to A4) ..................................................................... 16
DLL Reset bit (A8) ..................................................................................... 16
Mode Register/Extended Mode register change bits (BA0, BA1).............. 16
Extended Mode Register field .................................................................... 16
Reserved field ............................................................................................ 16
OPERATION MODE ................................................................................................................. 17
8.1
8.2
8.3
8.4
Simplified Truth Table ................................................................................................... 17
Function Truth Table ..................................................................................................... 18
Function Truth Table for CKE ....................................................................................... 21
Simplified Stated Diagram ............................................................................................ 22
Absolute Maximum Ratings .......................................................................................... 23
Recommended DC Operating Conditions .................................................................... 23
Capacitance .................................................................................................................. 24
Leakage and Output Buffer Characteristics .................................................................. 24
DC Characteristics ........................................................................................................ 25
AC Characteristics and Operating Condition ................................................................ 26
AC Test Conditions ....................................................................................................... 27
Table 1: Input Slew Rate for DQ, DQS, and DM .......................................................... 30
Table 2: Input Setup & Hold Time Derating for Slew Rate ........................................... 30
Table 3: Input/Output Setup & Hold Time Derating for Slew Rate ............................... 30
Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate ................ 30
Table 5: Output Slew Rate Characteristics (X16 Devices only) ................................... 30
Table 6: Output Slew Rate Matching Ratio Characteristics ......................................... 31
Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins ......... 31
Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins .......... 32
System Notes:............................................................................................................... 33
Command Input Timing ................................................................................................ 35
Timing of the CLK Signals ............................................................................................ 35
Read Timing (Burst Length = 4) ................................................................................... 36
Write Timing (Burst Length = 4) .................................................................................... 37
DM, DATA MASK (W9412G6JH) ................................................................................. 38
Mode Register Set (MRS) Timing ................................................................................. 39
Publication Release Date: Nov. 29, 2011
Revision A03
9.
ELECTRICAL CHARACTERISTICS ......................................................................................... 23
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10.
SYSTEM CHARACTERISTICS FOR DDR SDRAM ................................................................. 30
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.
TIMING WAVEFORMS ............................................................................................................. 35
11.1
11.2
11.3
11.4
11.5
11.6
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W9412G6JH
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
11.23
11.24
11.25
11.26
12.
13.
12.1
Extend Mode Register Set (EMRS) Timing .................................................................. 40
Auto-precharge Timing (Read Cycle, CL = 2) .............................................................. 41
Auto-precharge Timing (Read cycle, CL = 2), continued ............................................. 42
Auto-precharge Timing (Write Cycle) .......................................................................... 43
Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ........................................................ 44
Burst Read Stop (BL = 8) ............................................................................................ 44
Read Interrupted by Write & BST (BL = 8) .................................................................. 45
Read Interrupted by Precharge (BL = 8) ..................................................................... 45
Write Interrupted by Write (BL = 2, 4, 8) ..................................................................... 46
Write Interrupted by Read (CL = 2, BL = 8) ................................................................ 46
Write Interrupted by Read (CL = 3, BL = 4) ................................................................ 47
Write Interrupted by Precharge (BL = 8) ..................................................................... 47
2 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 48
2 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 48
4 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 49
4 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 49
Auto Refresh Cycle ..................................................................................................... 50
Precharged/Active Power Down Mode Entry and Exit Timing .................................... 50
Input Clock Frequency Change during Precharge Power Down Mode Timing .......... 50
Self Refresh Entry and Exit Timing ............................................................................. 51
TSOP (TYPE II) 66L 400 mil......................................................................................... 52
Package Specification ............................................................................................................... 52
REVISION HISTORY ................................................................................................................ 53
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Publication Release Date: Nov. 29, 2011
Revision A03
W9412G6JH
1. GENERAL DESCRIPTION
W9412G6JH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words
4 banks
16 bits. W9412G6JH delivers a data bandwidth of up to
500M words per second (-4). To fully comply with the personal computer industrial standard,
W9412G6JH is sorted into the following speed grades: -4, -5, -5I, -5K and -6I. The -4 is compliant to
the DDR500/CL3 and CL4 specification. The -5/-5I/-5K grade parts are compliant to the DDR400/CL3
specification (the -5I industrial grade parts is guaranteed to support -40°C ≤ T
A
≤ 85°C, the -5K
automotive grade parts is guaranteed to support -40°C ≤ T
A
≤ 105°C). The -6I grade parts is compliant
to the DDR333/CL2.5 specification which is guaranteed to support -40°C ≤ T
A
≤ 85°C.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and
CLK
signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6JH is ideal for main memory in
high performance applications.
2. FEATURES
2.5V
0.2V
Power Supply for DDR400/333
2.4V~2.7V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and
CLK
)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6µS Refresh interval (4K/64 mS Refresh), @ 0°C
≤
T
A
≤
85°C
3.9µS Refresh interval (4K/16 mS Refresh), @ 85°C
<
T
A
≤
105°C
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
Note:
Not support self refresh function with T
A
> 85°C
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Publication Release Date: Nov. 29, 2011
Revision A03
W9412G6JH
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
MIN./MAX.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
-4
-
-
-
-
4 nS
12 nS
4 nS
12 nS
40 nS
48 nS
60 mA
-5/-5I/-5K
7.5 nS
12 nS
6 nS
12 nS
5 nS
12 nS
-
-
40 nS
50 nS
55 mA
-6I
7.5 nS
12 nS
6 nS
12 nS
6 nS
12 nS
-
-
42 nS
54 nS
50 mA
CL = 2.5
t
CK
Clock Cycle Time
CL = 3
CL = 4
t
RAS
t
RC
Active to Precharge Command Period
Active to Ref/Active Command Period
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
Burst Operation Read Current
Burst Operation Write Current
Auto Refresh Current
Self Refresh Current
I
DD0
I
DD1
I
DD4R
I
DD4W
Max.
Max.
Max.
Max.
Max.
75 mA
140 mA
135 mA
75 mA
2 mA
65 mA
120 mA
115 mA
70 mA
2 mA
55 mA
110 mA
100 mA
65 mA
2 mA
I
DD5
I
DD6
-5-
Publication Release Date: Nov. 29, 2011
Revision A03
