W9816G6CH
512K
×
2 BANKS
×
16 BITS SDRAM
Table of Content-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PART NUMBER INFORMATION................................................................................................ 3
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
10.
11.
12.
Power Up and Initialization ............................................................................................. 7
Programming Mode Register.......................................................................................... 7
Bank Activate Command ................................................................................................ 7
Read and Write Access Modes ...................................................................................... 7
Burst Read Command .................................................................................................... 8
Burst Write Command .................................................................................................... 8
Read Interrupted by a Read ........................................................................................... 8
Read Interrupted by a Write............................................................................................ 8
Write Interrupted by a Write............................................................................................ 8
Write Interrupted by a Read............................................................................................ 8
Burst Stop Command ..................................................................................................... 9
Addressing Sequence of Sequential Mode .................................................................... 9
Addressing Sequence of Interleave Mode ..................................................................... 9
Auto-precharge Command ........................................................................................... 10
Precharge Command.................................................................................................... 10
Self Refresh Command ................................................................................................ 10
Power Down Mode ....................................................................................................... 11
No Operation Command............................................................................................... 11
Deselect Command ...................................................................................................... 11
Clock Suspend Mode.................................................................................................... 11
TABLE OF OPERATING MODES ............................................................................................ 12
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 13
RECOMMENDED DC OPERATING CONDITIONS................................................................. 13
CAPACITANCE......................................................................................................................... 13
DC CHARACTERISTICS.......................................................................................................... 14
Publication Release Date: June 10, 2005
Revision A0
-1-
W9816G6CH
13.
14.
AC CHARACTERISTICS .......................................................................................................... 15
TIMING WAVEFORMS ............................................................................................................. 17
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16
14.17
14.18
14.19
14.20
14.21
14.22
14.23
14.24
14.25
14.26
15.
16.
15.1
Command Input Timing ................................................................................................ 17
Read Tming .................................................................................................................. 18
Control Timing of Input/Output Data............................................................................. 19
Mode Reqister Set Cycle .............................................................................................. 20
Interleaved Bank Read ................................................................................................. 21
Interleaved Bank Read ................................................................................................. 22
Interleaved Bank Read ................................................................................................. 23
Interleaved Bank Read ................................................................................................. 24
Interleaved Bank Write ................................................................................................. 25
Interleaved Bank Write ................................................................................................ 26
Page Mode Read ........................................................................................................ 27
Page Mode Read/Write ............................................................................................... 28
AutoPrecharge Read................................................................................................... 29
AutoPrecharge Write ................................................................................................... 30
AutoRefresh Cycle ...................................................................................................... 31
SelfRefresh Cycle........................................................................................................ 32
Bust Read and Single Write ........................................................................................ 33
PowerDown Mode ....................................................................................................... 34
Autoprecharge Timing ................................................................................................. 35
Autoprecharge Timing ................................................................................................. 36
Timing Chart of Write-to-Read Cycle .......................................................................... 37
Timing Chart of Burst Stop Cycle................................................................................ 37
Timing Chart of Burst Stop Cycle (Prechare Command) ............................................ 38
CKE/DQM Input Timing............................................................................................... 39
CKE/DQM Input Timing............................................................................................... 40
Self Refresh/Power Down Mode Exit Timing .............................................................. 41
50L-TSOP (II) 400 mill .................................................................................................. 42
PACKAGE DIMENSIONS ......................................................................................................... 42
REVISION HISTORY ................................................................................................................ 43
-2-
W9816G6CH
1. GENERAL DESCRIPTION
W9816G6CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
×
2 banks
×
16 bits. Using pipelined architecture and 0.13
µm
process technology,
W9816G6CH delivers a data bandwidth of up to 400M bytes per second (-5). For different applications
the W9816G6CH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to
200Mhz/CL3. The -6 parts can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3. For
handheld device application.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6CH is ideal for main memory in
high performance applications.
2. FEATURES
3.3 /3.3 +/- 10% power supply
524,288 words x 2 banks x 16 bits organization
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst read, Single Write Mode
Byte data controlled by UDQM and LDQM
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 50-pin, 400 mil TSOP II, using PB free with RoHS compliant.
3. PART NUMBER INFORMATION
PART NUMBER
SPEED (CL=3)
SELF REFRESH CURRENT (MAX.)
W9816G6CH-5
W9816G6CH-6
W9816G6CH-7
200MHz
166MHz
143MHz
2mA
2mA
2mA
-3-
Publication Release Date: June 10, 2005
Revision A0
W9816G6CH
4. PIN CONFIGURATION
V
CC
DQ0
DQ1
V
SS
Q
DQ2
DQ3
V
CC
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
CC
Q
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
CC
Q
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
CC
Q
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
-4-
W9816G6CH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
20−24,
27−32
19
A0−A10
BA
Address
Bank Select
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
Select bank to activate during row address latch time,
or bank to read/write during column address latch
time.
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
DQ0−DQ15
42, 43, 45, 46,
48, 49
18
CS
Data Input/
Output
Chip Select
17
16
15
36, 14
RAS
Command input. When sampled at the rising edge of
Row Address
the clock,
RAS
,
CAS
and
WE
define the operation
Strobe
to be executed.
Column
Address Strobe Referred to
RAS
Write Enable
Input/Output
Mask
Clock Inputs
Clock Enable
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Ground for input buffers and logic circuit inside
DRAM.
CAS
WE
UDQM/
LDQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
35
34
1, 25
26, 50
7, 13, 38, 44,
4, 10, 41, 47
33, 37
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Power (+3.3V) Separated power from V
CC
, used for output buffers to
for I/O buffer improve noise immunity.
Ground for I/O Separated ground from V
SS
, used for output buffers
to improve noise immunity.
buffer
No Connection
No connection. (NC pin should be connected to GND
or floating)
-5-
Publication Release Date: June 10, 2005
Revision A0
模拟与混合信号
