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X80000Q32I

5-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32, 7 X 7 MM, 0.65 MM PITCH, QFN-32

器件类别:电源/电源管理    电源电路   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Renesas(瑞萨电子)
零件包装代码
QFN
包装说明
7 X 7 MM, 0.65 MM PITCH, QFN-32
针数
32
Reach Compliance Code
not_compliant
ECCN代码
EAR99
可调阈值
YES
模拟集成电路 - 其他类型
POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码
S-XQCC-N32
JESD-609代码
e0
长度
7 mm
信道数量
5
功能数量
1
端子数量
32
最高工作温度
85 °C
最低工作温度
-40 °C
封装主体材料
UNSPECIFIED
封装代码
VQCCN
封装形状
SQUARE
封装形式
CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
0.85 mm
最大供电电压 (Vsup)
14 V
最小供电电压 (Vsup)
10 V
标称供电电压 (Vsup)
12 V
表面贴装
YES
温度等级
INDUSTRIAL
端子面层
TIN LEAD
端子形式
NO LEAD
端子节距
0.65 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
7 mm
文档预览
®
X80000, X80001
Data Sheet
March 18, 2005
FN8148.0
Smart Power Plug™ Penta-Power
Sequence Controller with Hot Swap
The X80000 contains three major functions: a power
communications controller, a power sequencing controller,
and a hotswap controller.
The power communications controller allows smart power
supply control via the backplane using the SMBus protocol.
The system can check for voltage, current, and
manufacturing ID compliance before board insertion. The
power distribution network can monitor the status of the
negative voltage supply, DC voltage supplies, and hardshort
events by accessing the Fault Detection Register and
General Purpose EEPROM of the device. Each device has a
unique slave address for identification.
The power sequencer controller time sequences up to five
DC-DC modules. The X80000 allows for various hardwired
configurations, either parallel or relay sequencing modes.
The power good, enable and voltage good signals provide
for flexible DC-DC timing configurations. Each voltage
enable signal has a programmable delay. In addition, the
voltage good signals can be monitored remotely via the fault
detection register (thru the SMBus).
The hot swap controller allows a board to be safely inserted
and removed from a live backplane without turning off the
main power supply. The X80000 family of devices offers a
modular, power distribution approach by providing flexibility
to solve the hotswap and power sequencing issues for
insertion, operations, and extraction. Hardshort Detection
and Retry with Delay, Noise filtering, Insertion Overcurrent
Bypass, and Gate Current selection are some of the
programmable features of the device.
During insertion, the gate of an external power MOSFET is
clamped low to suppress contact bounce. The
undervoltage/overvoltage circuits and the power on reset
circuitry suppress the gate turn on until the mechanical
bounce has ended. The X80000 turns on the gate with a
user set slew rate to limit the inrush current and incorporates
an electronic circuit breaker set by a sense resistor. After the
load is successfully charged, the PWRGD signal is asserted;
indicating that the device is ready to power sequence the
DC-DC power bricks.
Features
• Integrates Three Major Functions
- Smart Power Plug communications
- Programmable power sequencing
- Programmable Hot Swap controller
• Smart Power Plug™
- Intelligent board insertion allows verification of board
and power supply resources prior to system insertion.
- Fault detection register records the cause of the faults
- Soft extraction
- Soft re-insertion
- Remote gate shutdown/turn on
- Power ID/manufacturing ID memory (2kb of EEPROM)
• Programmable Power Sequencing
- Sequence up to 5 DC/DC converters.
- Four independent voltage enable pins
- Four programmable time delay circuits
- Soft Power Sequencing - restart sequence without
power cycling.
• Hot Swap Controller
- Programmable overvoltage and undervoltage protection
- Undervoltage lockout for battery/redundant supplies
- Programmable slew rate for external FET gate control
- Electronic circuit breaker - overcurrent detection and
gate shut-off
- Programmable overcurrent limit during Insertion
- Programmable hardshort retry with retry failure flag
- Typically operates from -30V to -80V. Tolerates
transients to -200V (limited by external components)
• Available Packages
- 32-lead Quad No-Lead Frame (QFN)
Applications
• -48V Hot Swap Power Backplane/Distribution Central
Office, Ethernet for VOIP
• Card Insertion Detection
• Power Sequencing DC-DC/Power Bricks
• IP Phone Applications
• Databus Power Interfacing
• Custom Industrial Power Backplanes
• Distributed Power Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X80000, X80001
Pinout
X80000, X80001
(7X7 QFN)
TOP VIEW
BATT-ON
PWRGD
Ordering Information
PART
NUMBER
X80000Q32I
OV
74.9
68.0
UV1
42.4
42.4
UV2
33.2
33.2
TEMP
RANGE
I
I
PKG
32 Ld
QFN
32 Ld
QFN
PART
MARK
80000I
80001I
MRH
I
GQ0
I
GQ1
FAR
NC
V
EE
X80001Q32I
V
RGO
A0
V4GOOD
EN4
V3GOOD
EN3
V2GOOD
EN2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
(7mm x 7mm)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
NC
MRC
WP
RESET
V1GOOD
EN1
SCL
SDA
GATE
DRAIN
V
DD
V
EE
Typical Application
Back-
Plane
DC-DC
Module
1
ON/OFF
DC-DC
Module
2
ON/OFF
V
UV/OV
SENSE
NC
A1
X80000
X80001
SCL
SDA
Insert
Control
-48V
RTN
R5
30K
1%
R4
182K
1%
V
UV/OV
OV=71V
UV=37V
V
DD
R6
10K
1%
EN1
EN2
EN3
Opto-
Isolation
SCL
SDA
MRH
PWRGD
V1GOOD
V2GOOD
V3GOOD
DC-DC
Module
3
ON/OFF
DC-DC
Module
4
ON/OFF
V1
V2
V3
V
EE
SENSE GATE DRAIN
12V
4.7V
Rs
-48V
0.02Ω
5%
Q1
IRFR120
0.1µF
100 4.7K
3.3n
100K
V4
2
FN8148.0
March 18, 2005
X80000, X80001
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Voltage on given pin (Hot Side Functions):
V
ov/uv pin
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
SENSE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mV + V
EE
V
EE
pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80V
DRAIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48V + V
EE
PWRGD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V
EE
GATE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
+ V
EE
FAR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + V
EE
MRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
BATT_ON pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
Voltage on given pin (Cold Side Functions):
ENi pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
ViGOOD pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
SDA, SCL, WP, A0, A1 pins . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
MRC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
IGQ1 and IGQ0 pins . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + V
EE
V
DD
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V + V
EE
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Electrical Specifications
SYMBOL
DC CHARACTERISTICS
V
DD
I
DD
V
RGO
I
RGO
I
GATE
Standard Settings
Over the recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Operating Range
Supply Current
Regulated 5V output
V
RGO
current output
Gate Pin Current
Gate Drive On,
V
GATE
= V
EE
,
V
SENSE
= V
EE
(sourcing)
V
GATE
- V
EE
= 3V
V
SENSE
-V
EE
= 0.1V (sinking)
I
RGO
= 10µA
10
12
2.5
14
5
5.5
50
V
mA
4.5
µA
µA
46.2
52.5
58.8
9
V
DD
-0.01
0.9
V
EE
+ 4
1
V
DD
1.1
V
EE
+ 5
V
EE
+ 2
mA
V
V
V
V
µA
µA
V
GATE
V
PGA
V
IHB
V
ILB
I
LI
I
LO
External Gate Drive (Slew Rate Control)
Power Good Threshold (PWRGD High to Low)
Voltage Input High (BATT_ON)
Voltage Input Low (BATT_ON)
Input Leakage Current (MRH, MRC)
Output Leakage Current
(V1GOOD, V2GOOD, V3GOOD, V4GOOD,
RESET)
Input LOW Voltage (MRH, MRC, IGQ0, IGQ1)
Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1)
I
GATE
= 50µA
Referenced to V
EE
V
UV1
< V
UV/OV
< V
OV
V
IL
= GND to V
CC
All ENi = V
RGO
for i = 1 to 4
10
10
V
IL
V
IH
-0.5 +
V
EE
(V
EE
+ 5)
x 0.7
(V
EE
+ 5)
x 0.3
(V
EE
+ 5)
+ 0.5
V
V
3
FN8148.0
March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL
V
OL
Standard Settings
Over the recommended operating conditions unless otherwise specified.
(Continued)
PARAMETER
Output LOW Voltage
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD, FAR, PWRGD)
Output Capacitance
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD, FAR)
TEST CONDITIONS
I
OL
= 4.0mA
MIN
TYP
MAX
V
EE
+ 0.4
UNIT
V
C
OUT
(Note 1)
V
OUT
= 0V
8
pF
C
IN
(Note 1) Input Capacitance (MRH, MRC)
V
OC
V
OCI
Overcurrent threshold
Overcurrent threshold (Insertion)
V
IN
= 0V
V
OC
= V
SENSE
- V
EE
V
OC
= V
SENSE
- V
EE
PWRGD = HIGH
Initial Power Up condition
45
135
50
150
6
55
165
pF
mV
mV
V
OVR
Overvoltage threshold (rising)
X80000 Referenced to V
EE
X80001
3.85
3.49
3.90
3.54
3.95
3.59
V
V
V
OVF
Overvoltage threshold (falling)
X80000 Referenced to V
EE
X80001
3.82
3.46
Referenced to V
EE
BATT-ON = V
EE
Referenced to V
EE
BATT-ON = V
RGO
Referenced to V
EE
Referenced to V
EE
Referenced to V
EE
Referenced to V
EE
Referenced to V
EE
Referenced to V
EE
2.19
2.16
1.71
1.68
0.9
1.2
3.87
3.51
2.24
2.21
1.76
1.73
1
1.3
V
RGO
÷ 2
3.92
3.56
2.29
2.26
1.81
1.78
1.1
1.4
V
V
V
V
V
V
V
V
V
V
V
V
V
UV1R
V
UV1F
V
UV2R
V
UV2F
V
DRAINF
V
DRAINR
V
TRIP1
(Note 1)
V
TRIP2
(Note 1)
V
TRIP3
(Note 1)
V
TRIP4
(Note 1)
Undervoltage 1 threshold (rising)
Undervoltage 1 threshold (falling)
Undervoltage 2 threshold (rising)
Undervoltage 2 threshold (falling)
Drain sense voltage threshold (falling)
Drain sense voltage threshold (rising)
EN1 Trip Point Voltage
EN2 Trip Point Voltage
EN3 Trip Point Voltage
EN4 Trip Point Voltage
AC CHARACTERISTICS
t
FOC
t
FUV
t
FOV
t
VFR
t
BATT_ON
t
MRC
t
MRH
t
MRCE
t
MRCD
t
MRHE
Sense High to Gate Low
Under Voltage conditions to Gate Low
Overvoltage Conditions to Gate Low
Overvoltage/undervoltage failure recovery time to V
DD
does not drop below 3V, No
Gate =1V.
other failure conditions.
Delay BATT_ON Valid
Minimum time high for reset valid on the MRC pin
Minimum time high for reset valid on the MRH pin
Delay from MRC enable to PWRGD HIGH
Delay from MRC disable to PWRGD LOW
Delay from MRH enable to Gate Pin LOW
No Load
Gate is On, No Load
I
GATE
= 60µA, No Load
5
5
1.0
200
1.0
1.6
1.6
400
2.4
1.5
0.5
1.0
1.2
2.5
1
1.5
1.6
100
3.5
1.5
2
2
µs
µs
µs
µs
ns
µs
µs
µs
ns
µs
4
FN8148.0
March 18, 2005
X80000, X80001
Electrical Specifications
SYMBOL
t
MRHD
t
RESET_E
t
QC
Standard Settings
Over the recommended operating conditions unless otherwise specified.
(Continued)
PARAMETER
Delay from MRH disable to GATE reaching 1V
Delay from PWRGD or ViGOOD to RESET valid
LOW
Delay from IGQ1 and IGQ0 to valid Gate pin
current
TSC1 = 0; TSC0 = 0
TF1 = 0; TF0 = 1
90
4.5
45
TPOR1 = 0; TPOR0 = 0
90
100
5
50
100
50
Gate = V
DD
Gate = V
DD
Drain = V
EE
Drain = V
EE
1
1
1
1
TEST CONDITIONS
I
GATE
= 60µA, No Load
MIN
1.8
TYP
MAX
2.6
1
1
110
5.5
55
110
UNIT
µs
µs
µs
ms
µs
ms
ms
ns
µs
µs
µs
µs
t
SC_RETRY
Delay between retries
t
NF
t
DPOR
t
SPOR
t
TO
t
PDHLPG
(Note 1)
t
PDLHPG
(Note 1)
t
PGHLPG
(Note 1)
t
PGLHPG
(Note 1)
NOTE:
1. This parameter is based on characterization data.
Noise Filter for Overcurrent
Device Delay before Gate assertion
Delay after PWRGD and all ViGOOD signals are
active before RESET assertion
ViGOOD turn off time
Delay from Drain good to PWRGD LOW
Delay from Drain fail to PWRGD HIGH
Delay from Gate good to PWRGD LOW
Delay from Gate fail to PWRGD HIGH
Equivalent A.C. Output Load Circuit
5V
5V
5V
4.6kΩ
RESET
FAR
PWRGD
30pF
4.6kΩ
V1GOOD,
V2GOOD,
V3GOOD,
30pF
V4GOOD,
4.6kΩ
SDA
30pF
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
Standard output load
5
FN8148.0
March 18, 2005
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