xr
OCTOBER 2005
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.2.2
GENERAL DESCRIPTION
The XR16L2751
1
(2751) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes 2 additional capabilities over the
XR16L2750: Intel and Motorola data bus selection
and a “PowerSave” mode to further reduce sleep
current to a minimum during sleep mode. The 2751’s
register set is compatible to the ST16C2550 and
XR16C2850 but with added functions. It supports the
Exar’s enhanced features of 64 bytes of TX and RX
FIFOs, programmable FIFO trigger level, FIFO level
counters, automatic hardware and software flow
control, automatic RS-485 half duplex direction
control with programmable turn-around delay, and a
complete modem interface. Onboard registers
provide the user with operational status and data
error tags. An internal loopback capability allows
onboard diagnostics. Independent programmable
baud rate generator is provided in each UART
channel to support data rates up to 6.25 Mbps.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787
FEATURES
•
2.25 to 5.5 Volt Operation
•
5 Volt Tolerant Inputs
•
Functionally Compatible to ST16C2550 and
XR16C2850 with 4 additional inputs
•
Intel or Motorola Data Bus Interface Select
•
Two Independent UARTs
■
■
■
■
■
■
■
■
■
■
Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,
and 3 Mbps at 2.5 Volt with 8X sampling rate
64 bytes of Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Programmable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Selectable RTS Flow Control Hysteresis.
Automatic Software (Xoff/Xon) Flow Control
Automatic RS-485 2-wire Half-duplex Direction
Control to the Transceiver via RTS#
Full Modem Interface
Infrared Receive and Transmit Encoder/
decoder
APPLICATIONS
•
PowerSave Feature reduces sleep current to 15
µA at 3.3 Volt
•
Portable and Battery Operated Appliances
•
Wireless Access Servers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Telecommunication Network Routers
•
Factory Automation and Process Controls
F
IGURE
1. XR16L2751 B
LOCK
D
IAGRAM
•
Device Identification
•
Crystal or external clock input
•
Industrial and Commercial Temperature ranges
•
48 TQFP Package (7 x 7 x 1.0 mm)
PwrSave
A2:A0
D7:D0
IOR# (VCC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (logic 0)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset (Reset#)
16/68#
CLKSEL
HDCNTL#
Intel or
Motorola
Data Bus
Interface
*5 Volt Tolerant Inputs
(Except XTAL1)
2.25 to 5.5 Volt VCC
GND
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
64 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
2751BLK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
xr
REV. 1.2.2
TXRDYA#
48
47
46
45
44
43
42
41
40
39
38
37
HDCNTL#
DSRA#
CDA#
VCC
D4
D3
D2
D1
D0
CTSA#
RIA#
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
PWRSAVE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
CLKSEL
XR16L2751
48-pin TQFP
(16 Mode )
31
30
29
28
27
26
25
XTAL1
XTAL2
RXRDYB#
RTSB#
CTSB#
CDB#
DSRB#
16/68#
GND
IOW#
IOR#
RIB#
VCC
TXRDYA#
48
47
46
45
44
43
42
41
40
39
38
37
HDCNTL#
DSRA#
CDA#
VCC
D4
D3
D2
D1
D0
CTSA#
RIA#
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CS#
A3
PWRSAVE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
RESET#
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
IRQ#
INTB
A0
A1
A2
CLKSEL
XR16L2751
48-pin TQFP
(68 Mode )
31
30
29
28
27
26
25
XTAL1
XTAL2
RXRDYB#
RTSB#
CTSB#
DSRB#
16/68#
CDB#
GND
R/W#
VCC
RIB#
GND
ORDERING INFORMATION
P
ART
N
UMBER
XR16L2751CM
XR16L2751IM
P
ACKAGE
48-Lead TQFP
48-Lead TQFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
2
xr
REV. 1.2.2
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Description
N
AME
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes
read strobe (active low). The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines [A2:A0],
puts the data byte on the data bus to allow the host processor to read it on the rising
edge.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not
used and should be connected to VCC.
When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write
strobe (active low). The falling edge instigates the internal write cycle and the rising
edge transfers the data byte on the data bus to an internal register pointed by the
address lines.
When 16/68# pin is LOW, the Motorola bus interface is selected and this input
becomes read (HIGH) and write (LOW) signal.
When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A
in the device.
When 16/68# pin is LOW, this input becomes the chip select (active low) for the
Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B
in the device.
When 16/68# pin is LOW, this input becomes address line A3 which is used for chan-
nel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1
selects channel B.
When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A inter-
rupt output. The output state is defined by the user through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3]
is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output becomes device
interrupt output (active low, open drain). An external pull-up resistor is required for
proper operation.
IOW#
(R/W#)
15
I
CSA#
(CS#)
10
I
CSB#
(A3)
11
I
INTA
(IRQ#)
30
O
3
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Pin Description
N
AME
INTB
48-TQFP
P
IN
#
29
T
YPE
O
D
ESCRIPTION
xr
REV. 1.2.2
When 16/68# pin is HIGH for Intel bus interface, this output becomes channel B inter-
rupt output. The output state is defined by the user and through the software setting
of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when
MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this output is not used and will
stay at logic zero level. Leave this output unconnected.
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel A.
UART channel A Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel A.
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B.
UART channel B Receiver Ready (active low). This output provides the RX FIFO/
RHR status for receive channel B.
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
43
31
6
18
O
O
O
O
MODEM OR SERIAL I/O INTERFACE
TXA
7
O
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
UART channel A Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles at logic 0 but can be
inverted by software control prior going to the decoder, see MCR[6] and FCTR[2].
UART channel A Request-to-Send (active low) or general purpose output. This out-
put must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
UART channel A Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be con-
nected to VCC when not used.
UART channel A Data-Terminal-Ready (active low) or general purpose output.
UART channel A Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
Output Port 2 Channel A - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTA is set to the level
mode and OP2A# output LOW. When MCR[3] is set to a logic 0, INTA is set to the
three state mode and OP2A# is HIGH. See MCR[3]. This output must not be used as
a general output when the interrupt output is used else it will disturb the INTA output
functionality.
RXA
5
I
RTSA#
33
O
CTSA#
38
I
DTRA#
DSRA#
CDA#
RIA#
OP2A#
34
39
40
41
32
O
I
I
I
O
4
xr
REV. 1.2.2
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Pin Description
N
AME
TXB
48-TQFP
P
IN
#
8
T
YPE
O
D
ESCRIPTION
UART channel B Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
UART channel B Receive Data or infrared receive data. Normal receive data input
must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted
by software control prior going in to the decoder, see MCR[6] and FCTR[2].
UART channel B Request-to-Send (active low) or general purpose output. This port
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see
FCTR[3] and EMSR[3].
UART channel B Clear-to-Send (active low) or general purpose input. It can be used
for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to
VCC when not used.
UART channel B Data-Terminal-Ready (active low) or general purpose output.
UART channel B Data-Set-Ready (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
UART channel B Carrier-Detect (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART
UART channel B Ring-Indicator (active low) or general purpose input. This input
should be connected to VCC when not used. This input has no effect on the UART.
Output Port 2 Channel B - The output state is defined by the user and through the
software setting of MCR[3]. When MCR[3] is set to a logic 1, INTB is set to the level
mode and OP2B# output LOW. When MCR[3] is set to a logic 0, INTB is set to the
three state mode and OP2B# is HIGH. See MCR[3]. This output must not be used as
a general output when the interrupt output is used else it will disturb the INTB output
functionality.
RXB
4
I
RTSB#
22
O
CTSB#
23
I
DTRB#
DSRB#
CDB#
RIB#
OP2B#
35
20
16
21
9
O
I
I
I
O
ANCILLARY SIGNALS
XTAL1
XTAL2
PwrSave
13
14
12
I
O
I
Crystal or external clock input. This input is not 5V tolerant.
Crystal or buffered clock output. This output may be use to drive a clock buffer which
can drive other device(s).
PowerSave (active high). This feature isolates the 2751’s data bus interface from the
host preventing other bus activities that cause higher power drain during sleep mode.
See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.
Intel or Motorola Bus Select.
When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus
type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motor-
ola bus type of interface.
Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is
only sampled during power up or a reset. Connect to VCC for divide by 1 and GND
for divide by 4. MCR[7] can override the state of this pin following a reset or initializa-
tion. See MCR bit-7 and
Figure 6
in the Baud Rate Generator section.
16/68#
24
I
CLKSEL
25
I
5
FPGA/CPLD
