[讨论] Modesim se 6.2 仿真问题

eeleader   2010-6-23 13:21 楼主

当利用 modelsim se 6.2b 运行 test文件 怎么对象框中没有信号列表?这样add wave 就会现No objects found matching '/test_counter/*'的错误
想知道是哪里出了问题

下面是test_counterd原代码
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
  begin
    clk = 0;
    #10 forever #10 clk = !clk;
  end
  
initial // Test stimulus
  begin
    rst = 0;
    #5 rst = 1;
    #4 rst = 0;
    #50000 $stop;
  end
  
initial
    $monitor($stime,, rst,, clk,,, count);
   
endmodule   

下面是 counter.v的原代码
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count   =  1;
parameter tpd_reset_to_count =  1;

function [7:0] increment;
input [7:0] val;
reg [3:0] i;
reg carry;
  begin
    increment = val;
    carry = 1'b1;
    /*
     * Exit this loop when carry == zero, OR all bits processed
     */
    for (i = 4'b0; ((carry == 4'b1) || (i <= 7));  i = i+ 4'b1)
       begin
         increment = val ^ carry;
         carry = val & carry;
       end
  end      
endfunction
always @ (posedge clk or posedge reset)
  if (reset)
     count = #tpd_reset_to_count 8'h00;
  else
     count <= #tpd_clk_to_count increment(count);
/*
* To make module counter synthesizeable, use the following
*  alternate form of the always block:
*/
/***********************************************
always @ (posedge clk or posedge reset)
  if (reset)
     count <= 8'h00;
  else
     count <= count + 8'h01;
***********************************************/
endmodule

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