[求助] 新人第一次用quartus

module test;
reg [14*8:1] str_v;
initial 
begin 
str_v="hello";
$display ("%s is stored as %h",str_v,str_v);
str_v={str_v,"!!!"};
$display ("%s is stored as %h",str_v,str_v);
end
endmodule

输入上述代码后不仿真，只想它输出文字。编译也没错。可是输出结果在哪找呢

可以学习一下modelsim

了解一下Verilog HDL....................