can't resolve multiple constant drivers for net cnt_count[3]

lidabao 2013-7-25 00:33 楼主

请求大侠以下程序cnt_count哪边出错了啊
module tx_uart(clk_100, rst, tx_shuju, tx_flag, tx_data, tx_finish_flag);

input clk_100;
input rst;
input tx_flag;
input [7:0]tx_shuju;

output tx_data;
output tx_finish_flag;

reg tx_finish_flag;
reg tx_data;

parameter idle       = 5'b00001;
parameter send_start  = 5'b00010;
parameter send_data = 5'b00100;
parameter send_parity = 5'b01000;
parameter send_stop = 5'b10000;

reg [4:0]crt_state;
reg [4:0]next_state;

reg start_trig;
reg start_en;

always@(posedge clk_100)
if(!rst)
start_trig <= 1'b0;
else
start_trig <= tx_flag;

reg [3:0]cnt_count;
reg [9:0]cnt_time;
always@(posedge clk_100)
if(!rst)
cnt_time <= 10'd0;
else if(start_en)
cnt_time <= 10'd0;
else if(cnt_count <= 4'd13)
begin
if(cnt_time == 10'd867)
cnt_time <= 10'd0;
else
cnt_time <= cnt_time + 1'b1;
end
else if(cnt_count > 4'd13)
cnt_time <= cnt_time;
else
cnt_time <= cnt_time;

reg [7:0]shift_data;

always@(posedge clk_100)
if(!rst)
shift_data <= 8'hff;
else if(start_en)
shift_data <= tx_shuju;
else if((cnt_time == 10'd0) && (crt_state == send_data))
shift_data <= shift_data;
else if((cnt_time == 10'd867) && (crt_state == send_data))
shift_data <= {1'b1, shift_data[7:1]};
else
shift_data <= shift_data;

reg parity_cnt;
always@(posedge clk_100)
if(!rst)
parity_cnt <= 1'b0;
else if(crt_state == idle)
parity_cnt <= 1'b0;
else if(crt_state == send_data)
begin
if(cnt_time == 10'd500)
parity_cnt <= parity_cnt + shift_data[0];
else
parity_cnt <= parity_cnt;
end
else
parity_cnt <= parity_cnt;

always@(posedge clk_100)
if(!rst)
cnt_count <= 4'd15;
else if(start_en)
cnt_count <= 4'd0;
else if(cnt_count <= 4'd13)
begin
if(cnt_time == 10'd867)
cnt_count <= cnt_count + 1'b1;
else
cnt_count <= cnt_count;
end
else if(cnt_count > 4'd13)
cnt_count <= 4'd15;

//reg [3:0]cnt_count1;
//always@(posedge clk_100)
// if(!rst)
// cnt_count1 <= 4'd0;
// else
// cnt_count1 <= cnt_count;
//
//
always@(posedge clk_100)
if(!rst)
start_en <= 1'b0;
else
begin
if((tx_flag) && (!start_trig))
start_en <= 1'b1;
else
start_en <= 1'b0;
end

always@(posedge clk_100)
if(!rst)
crt_state <= idle;
else
crt_state <= next_state;

always@(posedge clk_100)
begin
case(crt_state)
idle :
begin
if(start_en)
next_state = send_start;
else
next_state = crt_state;
end

send_start :
begin
if((cnt_count == 4'd0) && (cnt_time == 10'd867))
next_state = send_data;
else
next_state = crt_state;
end

send_data :
begin
if((cnt_count == 4'd8) && (cnt_time == 10'd867))
next_state = send_parity;
else
next_state = crt_state;
end
send_parity :
begin
if((cnt_count == 4'd9) && (cnt_time == 10'd867))
next_state = send_stop;
else
next_state = crt_state;
end

send_stop :
begin
if((cnt_count = 4'd10) && (cnt_time == 10'd500))
next_state = idle;
else
next_state = crt_state;
end

default :
next_state = idle;
endcase
end

always@(posedge clk_100)
if(!rst)
tx_data <= 1'b1;
else if(crt_state == idle)
tx_data <= 1'b1;
else if(crt_state == send_data)
tx_data <= shift_data[0];
else if(crt_state == send_parity)
tx_data <= parity_cnt;
else if(crt_state == send_stop)
tx_data <= 1'b1;
else
tx_data <= 1'b1;

always@(posedge clk_100)
if(!rst)
tx_finish_flag <= 1'b0;
else if(crt_state == send_stop)
tx_finish_flag <= 1'b1;
else
tx_finish_flag <= 1'b0;

endmodule