这个相位检测算法可以用verilog hdl描述吗?里面涉及太多延时或计时,头都大了。
哪位大侠帮帮我呀,这里附上用汇编做的程序,根据实际需要,我要把它用verilog hdl给描述出来。
;//==================================
PHASE_DETECT:
MOV PHASE_NUMBER,#10H ;//相位调节次数=10H
MOV A,U414_STATUS
JB ACC.5,PHASE_DETECT_10
MOV A,U414_STATUS
SETB ACC.5 ;//EHT INH=0(高压板上的绿灯灭)
MOV U414_STATUS,A
MOV DPTR,#0CFFFH ;//选通U413
MOVX @DPTR,A
MOV A,SOL_STATUS
SETB ACC.7 ;//GREEN RELAY 合上
MOV SOL_STATUS,A
MOV DPTR,#7FFFH
MOVX @DPTR,A
SETB FRT_PRT_RDY
MOV A,FAULT_UNIT
SETB ACC.4 ;//EHT_ON
MOV FAULT_UNIT,A
PHASE_DETECT_10:
MOV R2,#00H
MOV R3,#00H
MOV R4,#00H
DJNZ R4,$
MOV R4,#00H ;//22H
DJNZ R4,$
MOV R1,PHASE_NUMBER ;//相位调节次数
PHASE_DETECT_90:
MOV R4,#39H ;//R4=17H(39H)
JB PHASE_REQUEST,PHASE_DETECT_20 ;//有相位请求吗?
RET
PHASE_DETECT_20:
JB T1,$
JNB T1,$
CLR EA
CLR PHASE_CLAMP ;//P14=0,PHASE SWITCH OFF
DJNZ R4,$
SETB PHASE_CLAMP ;//P14=1,PHASE SWITCH ON
MOV R4,#1EH ;//R4=07H(14H)
DJNZ R4,$
CLR F0
MOV R4,#32H ;//R4=26H(40H)
PHASE_DETECT_40:
MOV DPTR,#0CFFFH ;//选通U413
MOVX A,@DPTR
JB ACC.1,PHASE_DETECT_30 ;//PHASE_ALIG="1"?OK,PHASE ALIGNED MUCH
DJNZ R4,PHASE_DETECT_40
SJMP PHASE_DETECT_50
PHASE_DETECT_30:
SETB F0
PHASE_DETECT_50:
MOV A,P1 ;//NO,PHASE ALIGNED LITTLE
ANL A,#0FCH
ORL A,#11H
MOV R6,A ;//保存调频系数--->R6
MOV R4,#12H
JB F0,PHASE_DETECT_60
MOV R4,#10H ;//F0=0,PHASE DIG LITTLE
INC R3
MOV A,PHASE_OFFSET
INC A
JZ PHASE_DETECT_70
MOV PHASE_OFFSET,A
SJMP PHASE_DETECT_70
PHASE_DETECT_60: ;//F0=1,PHASE DIG MUCH
INC R2
MOV A,PHASE_OFFSET
DEC A
JZ PHASE_DETECT_70
MOV PHASE_OFFSET,A
PHASE_DETECT_70:
MOV A,P1
ANL A,#0FCH
ORL A,R4
MOV R4,#02H ;//R4=01H(02H)
JB PHASE_REQUEST,PHASE_DETECT_80 ;//CHK IF PHASE_REQUEST=0
SETB EA
RET
PHASE_DETECT_80:
JB T1,$
JNB T1,$
MOV P1,A ;//P14=1,ON PHASE SWITCH
XCH A,R6
DJNZ R4,$
MOV P1,A ;//恢复调频系数--->P1
MOV R4,#25H ;//R4=0FH(25H)
DJNZ R4,$
DJNZ R1,PHASE_DETECT_90
CLR EA
MOV A,PHASE_NUMBER ;//PHASE ADJUST
CLR C
CPL A
INC A
ADD A,R2
MOV R2,#00H
JC PHASE_DETECT_A0
MOV A,PHASE_NUMBER ;//PHASE ADJUST
CPL A
INC A
ADD A,R3 ;//PHASE DIG LITTLE
MOV R3,#00H
JC PHASE_DETECT_B0
MOV DPTR,#0CFFFH ;//选通U413
MOVX A,@DPTR
CPL A
JB ACC.3,PHASE_DETECT_C0 ;//JET START
MOV A,SOL_STATUS
SETB ACC.7 ;//GREEN RELAY 合上
MOV SOL_STATUS,A
MOV DPTR,#7FFFH
MOVX @DPTR,A
SETB FRT_PRT_RDY
PHASE_DETECT_C0:
CALL FAULT_DISPLAY
SETB EA
RET
;//================================== ;//相位调节过大(相位调节过大时,绿灯不灭)
PHASE_DETECT_B0:
MOV A,U415_STATUS
JNB ACC.1,PHASE_DETECT_B1 ;//相位调制故障已存在吗?
SETB EA
RET
PHASE_DETECT_B1:
ORL A,#01H ;//充电故障灯亮,相位故障灯灭
;// ANL A,#0FBH
MOV U415_STATUS,A
MOV DPTR,#5FFFH ;//选通U414
MOVX @DPTR,A
MOV A,FAULT_UNIT
SETB ACC.1
CLR ACC.4
MOV FAULT_UNIT,A
MOV A,SOL_STATUS
SETB ACC.6 ;//黄灯亮
MOV SOL_STATUS,A
MOV DPTR,#7FFFH
MOVX @DPTR,A
MOV A,U414_STATUS
SETB ACC.2 ;//面板充电故障灯亮
MOV U414_STATUS,A
MOV DPTR,#0CFFFH ;//选通U413
MOVX @DPTR,A
SETB EA
RET
;//================================== ;//相位调节过小(相位调节过小时,绿灯不灭)
PHASE_DETECT_A0:
MOV A,U415_STATUS
JNB ACC.1,PHASE_DETECT_A1 ;//相位调制故障已存在吗?
SETB EA
RET
PHASE_DETECT_A1:
; ORL A,#04H ;//充电故障灯灭,相位故障灯亮
ANL A,#0FEH
MOV U415_STATUS,A
MOV DPTR,#5FFFH ;//选通U414
MOVX @DPTR,A
MOV A,FAULT_UNIT
SETB ACC.1
CLR ACC.4
MOV FAULT_UNIT,A
MOV A,SOL_STATUS
SETB ACC.6 ;//黄灯亮
MOV SOL_STATUS,A
MOV DPTR,#7FFFH
MOVX @DPTR,A
MOV A,U414_STATUS
SETB ACC.2 ;//面板充电故障灯亮
MOV U414_STATUS,A
MOV DPTR,#0CFFFH ;//选通U413
MOVX @DPTR,A
SETB EA
RET
MOV R4,#39H ;//R4=17H(39H)
JB PHASE_REQUEST,PHASE_DETECT_20 ;//有相位请求吗?
RET
PHASE_DETECT_20:
JB T1,$
JNB T1,$
CLR EA
CLR PHASE_CLAMP ;//P14=0,PHASE SWITCH OFF
DJNZ R4,$
SETB PHASE_CLAMP ;//P14=1,PHASE SWITCH ON
这一小段汇编程序如何用verilog hdl的循环语句实现
让人读汇编,还要帮编HDL,这也忒牛了吧?
再说设计项目具体化之后,想用HDL做的事未必能和参考程序一一对应,别人未必插得上手。
能求教的仅限于思路,具体的唯自己动手,方不枉学习一场。
实际上上面几贴把思路都已说了:
●利用时钟计数的办法实现延时
●用状态机的办法实现顺序控制
用VHDL写的状态机例子如下或可供参考,用什么语言无关,具体写法也随便,有此思路即可。
if rising_edge(clock) then
if (state = 0) then
任务[A];
state <= state + 1; -- 执行完本次state的任务[A]之后,即进入下次任务的准备
elsif (state = 1) then
if (条件[B]) then
cnt <= 100;
state <= state + 1; -- 等满足条件[B]之后,方进入下次任务的准备
end if;
elsif (state = 2) then
if (cnt > 0]) then
cnt <= cnt - 1;
else
state <= state + 1; -- 等待100个clock的延迟之后,进入下次任务的准备
end if;
elsif (state = 3) then
...
...
...
end if
end if