麻烦各位大神帮我看看。
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--Project3 --Toplevel.vhd --Boyuan Chen --12.11.14
-- top level
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Toplevel is
port (SW : in std_logic_vector(3 downto 0);
Clock : in std_logic;
Reset : in std_logic;
DY : in std_logic_vector(3 downto 0);
addx : out std_logic_vector(3 downto 0);
LED : out std_logic_vector(3 downto 0));
end Toplevel;
architecture Behavioral of Toplevel is
signal clk_temp : std_logic;
component Microcode is
port (SW : in std_logic_vector(3 downto 0);
Clock : in std_logic;
Reset : in std_logic;
DY : in std_logic_vector(3 downto 0);
addx : out std_logic_vector(3 downto 0);
LED : out std_logic_vector(3 downto 0));
end component;
component clockdiv is
Generic (NN :integer :=1 );
Port (clkin,clr : in STD_LOGIC;
clkout : out STD_LOGIC);
end component;
begin
U1: Microcode port map(SW=>SW, Clock=>clk_temp, reset=>reset,
DY=>DY, addx=>addx, LED=>LED);
U2: ClockDiv port map(clkin=>clock, clr=>reset, clkout=>clk_temp);
end Behavioral;
这是我的顶层
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--project3 --Microcode --Boyuan Chen --12.1.14
--Data Path & Controler
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity Microcode is
port (SW : in std_logic_vector(3 downto 0);
Clock : in std_logic;
Reset : in std_logic;
DY : in std_logic_vector(3 downto 0);
addx : out std_logic_vector(3 downto 0);
LED : out std_logic_vector(3 downto 0));
end Microcode;
architecture Behavioral of Microcode is
signal addi, dx: integer range 0 to 3;
signal Test : std_logic_vector(1 downto 0);
signal Natt : std_logic_vector(3 downto 0);
signal EnA, EnN, EnL,Wr : std_logic;
signal EnC : std_logic_vector(1 downto 0);
signal SelMux, SelAlu : std_logic_vector (1 downto 0);
signal Zf, Cf: std_logic;
signal X, Y, F, Kval, RegA, RegC, RegN, RegL: std_logic_vector(3 downto 0);
subtype MREC is std_logic_vector(19 downto 0);
type MSTORE is array (natural range<>) of MREC;
constant MROM : MSTORE :=(
"00"&"0000"&'0'&"00"&'1'&'0'&"11"&"10"&"0000"&'0',
"11"&"0000"&'0'&"00"&'0'&'0'&"10"&"11"&"0001"&'0',
"00"&"0000"&'1'&"00"&'0'&'0'&"10"&"10"&"0001"&'0',
"00"&"0000"&'0'&"00"&'1'&'1'&"10"&"10"&"0000"&'0',
"10"&"0000"&'0'&"00"&'0'&'0'&"00"&"00"&"0000"&'0',
"00"&"0000"&'0'&"01"&'0'&'0'&"10"&"00"&"0000"&'0',
"00"&"0000"&'0'&"00"&'1'&'1'&"00"&"00"&"0000"&'0',
"01"&"0100"&'1'&"00"&'0'&'0'&"01"&"10"&"0000"&'0');
Begin
--Microstore Rom
test <= MROM(addi)(19 downto 18);
natt <= MROM(addi)(17 downto 14);
EnA <= MROM(addi)(13);
EnC <= MROM(addi)(12 downto 11);
EnN <= MROM(addi)(10);
EnL <= MROM(addi)(9);
SelMux <= MROM(addi)(8 downto 7);
SelAlu <= MROM(addi)(6 downto 5);
Kval <= MROM(addi)(4 downto 1);
Wr <= MROM(addi)(0);
dx <= CONV_INTEGER(natt);
--Address Counter
Process(Reset,Clock)
begin
if reset = '1' then
addi <= 0;
elsif Clock'event and Clock ='1' then
addi <= addi +1;
if test = "01" then
addi <= dx; --always branch (next value in natt)
elsif test ="10" then
if cf = '1' then addi <= dx; --branch if c flag is high (next value in natt)
end if;
elsif test ="11" then
if zf = '1' then addi <= dx; --branch if z flag is high (next value in natt)
end if;
end if;
end if;
end process;
--RegA enable and load
Process(Reset,Clock)
begin
if reset = '1' then
RegA <= "0000";
elsif Clock'event and Clock = '1' then
if EnA = '1' then
RegA <= F;
end if;
end if;
End Process;
--RegC endable and load !!RegC represents RegD!!
Process(Reset,Clock)
begin
if reset = '1' then
RegC <= "0000";
elsif Clock'event and Clock = '1' then
if EnC = "10" then
RegC <= DY;
elsif EnC(0) <= '1' then
RegC <= F;
else RegC <= RegC;
end if;
end if;
End Process;
--RegN endable and load
Process(Reset,Clock)
begin
if reset = '1' then
RegN <= "0000";
elsif Clock'event and Clock = '1' then
if EnN = '1' then
RegN <= F;
end if;
end if;
End Process;
X <= RegN;
--RegL endable and load
Process(Reset,Clock)
begin
if reset = '1' then
RegL <= "0000";
elsif Clock'event and Clock = '1' then
if EnL = '1' then
RegL <= F;
end if;
end if;
End Process;
--multiplexer
Y <= RegA when SelMux = "00" else
RegC when SelMux = "01" else
Kval when SelMux = "10" else
Sw when SelMux = "11";
--Alu
process(X,Y,SelAlu)
variable temp : std_logic_vector (4 downto 0);
variable muxout : std_logic_vector(3 downto 0);
variable zf1 : std_logic;
begin
temp := "00000";
zf1 := '0';
muxout := "0000";
cf <= '0';
case SelAlu is
when "00" => temp := ('0' & X) + ('0' & Y); --addition
muxout := temp (3 downto 0);
cf <= temp(4);
when "01" => temp := ('0' & X) - ('0' & Y); --subtraction
muxout := temp (3 downto 0);
cf <= temp(4);
when "10" => muxout := Y; --F = Y
when "11" => muxout := X and Y; --bitwise AND
when others => muxout := x;
end case;
for i in 0 to 3 loop --z flag check
zf1 := muxout(i) or zf1;
end loop;
f <= muxout;
zf <= not zf1;
end process;
-- assign output values
LED <= RegL;
--convert integer to state address
ADDX <= conv_std_logic_vector(addi,4);
end Behavioral;
----------------------------------------------------------------------------------
--ClkWork --ClockDiv.vhd --boyuan chen --11.16.14
--2Hz Clock
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ClockDiv is
Generic (NN :integer :=12500000 );
Port ( clkin,clr : in STD_LOGIC;
clkout : out STD_LOGIC);
end ClockDiv;
architecture Behavioral of ClockDiv is
signal cnt : integer range 0 to NN-1;
signal clk : std_logic :='1';
begin
process(clkin,clr)
begin
if clr='1' then
cnt<=0; clk<='1';
elsif clkin'event and clkin='1' then
if cnt =NN-1 then
cnt<=0; clk<= not clk;
else
cnt<=cnt+1;
end if;
end if;
end process;
clkout <= clk;
end Behavioral;
当我跑behavioral simulation 的时候结果正常
然而当我跑post-route simulation的时候结果就出不来了
对了我用的是ise 14.7
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