跪求大神指点，目前在做xc95144xl的开发，但是之前师兄留下的程序，在做功能仿真的时候，出现的波形如下所示，没有变化
有没有大神可以指点一下，我该怎么办、、、(代码如下)
-- Company:
-- Engineer:
--
-- Create Date: 09:54:29 03/31/2008
-- Design Name:
-- Module Name: cpld_331 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cpld_331 is
port(
RESET :in std_logic;
-- MIC_RST :in std_logic;
PM5352_RST : out std_logic;
XR16C2850_RST : out std_logic;
Zi9001_RST1 : out std_logic;
Zi9001_RST2 : out std_logic;
IDT82P2282_RST : out std_logic;
-- ADD_INT : out std_logic;
PM5352_INT :in std_logic;
XR16C2850_INTA :in std_logic;
XR16C2850_INTB :in std_logic;
Zi9001_INT1 :in std_logic;
Zi9001_INT2 :in std_logic;
IDT82P2282_INT :in std_logic;
-- latch_rd_data: out STD_LOGIC_VECTOR(7 DOWNTO 0);
-- latch_wr_data: out STD_LOGIC_VECTOR(7 DOWNTO 0);
GPIO:in std_logic_vector(3 downto 0);
OE :out std_logic;
DIR :out std_logic;
AOI_RD :out STD_LOGIC;
AOI_WR :out STD_LOGIC;
AOI_D :inout STD_LOGIC_VECTOR(7 DOWNTO 0);
AOI_A :out STD_LOGIC_VECTOR(9 DOWNTO 0);
pm5352_cs:out std_logic;
xr16c2850_csa :out std_logic;
xr16c2850_csb :out std_logic;
idt82p2282_cs: out std_logic;
zi9001_1_cs:out std_logic;
zi9001_2_cs:out std_logic;
SP_CLK :IN STD_LOGIC;
SP_ACKn :out STD_LOGIC;
SP_ALEn :IN STD_LOGIC;
SP_CP_A0 :IN STD_LOGIC;
SP_DIR_A1 :IN STD_LOGIC;
SP_CS1n :IN STD_LOGIC;
SP_CS0n :IN STD_LOGIC;
SP_WR :IN STD_LOGIC;
SP_RD :IN STD_LOGIC;
SP_OEn :IN STD_LOGIC;
SP_AD :inout STD_LOGIC_VECTOR(7 DOWNTO 0);
------v35data and clk for test
clk_2M :in std_logic;
clk_out,data_v35: out std_logic;
-------v.35 control signal
RTS_DTE:out std_logic;
DTR_DTE:out std_logic;
RLPBK_DTE:out std_logic;
LLPBK_DTE:out std_logic;
CTS_DTE:in std_logic;
DCD_DTE:in std_logic;
DSR_DTE:in std_logic;
RI_DTE:in std_logic;
CTS_DCE:out std_logic;
DCD_DCE :out std_logic;
DSR_DCE :out std_logic;
RI_DCE:out std_logic;
RTS_DCE:in std_logic;
DTR_DCE:in std_logic;
RLPBK_DCE:in std_logic;
LLPBK_DCE:in std_logic
);
end cpld_331;
architecture Behavioral of cpld_331 is
signal ACK_sig : std_logic;
signal ACK_enable :std_logic;
SIGNAL RST_INn :std_logic;
signal PM5352_RST_reg : std_logic;
signal XR16C2850_RST_reg :std_logic;
signal Zi9001_RST1_reg : std_logic;
signal Zi9001_RST2_reg : std_logic;
signal IDT82P2282_RST_reg : std_logic;
signal ADDR_LATCH :std_logic_vector(10 downto 0);
SIGNAL CSn_END : STD_LOGIC;
SIGNAL AOI_DATA_LATCH : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL DATA_LATCH_EN : STD_LOGIC;
SIGNAL SP_AD_OUT_EN1,SP_AD_OUT_EN0 : STD_LOGIC;
--SIGNAL LOCAL_CSn: STD_LOGIC;
SIGNAL SP_D_LOW_LATCH_EN, SP_D_HI_LATCH_EN : STD_LOGIC;
SIGNAL SP_D_LATCH0,SP_D_LATCH1 : STD_LOGIC;
SIGNAL AOI_D_WR : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal rd_reg :std_logic;
signal wr_reg :std_logic;
SIGNAL LOCAL_CSn: STD_LOGIC;
--signal wr_en :std_logic;
--signal CARDID_REG :std_logic_vector(2 downto 0);
signal card_cs_reg : std_logic;
signal intternal_reg_cs : std_logic;
signal pm5352_cs_sig : std_logic;
signal xr16c2850_csa_sig : std_logic;
signal xr16c2850_csb_sig : std_logic;
signal idt82p2282_cs_sig : std_logic;
signal zi9001_1_cs_sig : std_logic;
signal zi9001_2_cs_sig : std_logic;
-------v.35 signal registers
signal RTS_DTE_reg : std_logic;
signal DTR_DTE_reg : std_logic;
signal RLPBK_DTE_reg : std_logic;
signal LLPBK_DTE_reg : std_logic;
signal CTS_DCE_reg : std_logic;
signal DCD_DCE_reg : std_logic;
signal DSR_DCE_reg : std_logic;
signal RI_DCE_reg : std_logic;
----------------------
signal counter: std_logic_vector(4 downto 0);
signal clk_64k: std_logic;
type style is(A,B,C,D,E,F,G,H);
signal sta:style;
begin
--latch_rd_data(7 downto 0)<=AOI_DATA_LATCH(7 downto 0);
--latch_wr_data(7 downto 0)<=AOI_D_WR(7 DOWNTO 0);
--RST_INn<=RESET and MIC_RST;
RST_INn<=RESET;
OE<='0';
DIR<= not SP_DIR_A1;
PROCESS(SP_CS0n)
BEGIN
IF SP_ALEn='0' OR RST_INn='0' THEN
LOCAL_CSn<='1';
ELSIF SP_CS0n'EVENT AND SP_CS0n='0' THEN
LOCAL_CSn<='0';
END IF;
END PROCESS;
----------------------------------------------------------------------ACK process
process(RST_INn,SP_CLK)
begin
if RST_INn='0' or SP_ALEn='0' then
ACK_enable<='1';
elsif rising_edge(SP_CLK) then
if SP_CS1n='0' then
ACK_enable<='0';
end if;
end if;
end process;
process(RST_INn,SP_CLK)
variable Q :std_logic_vector(1 downto 0);
begin
if RST_INn='0' or SP_ALEn='0' then
Q:=(others=>'0');
ACK_sig<='1';
elsif rising_edge(SP_CLK) then
if ACK_enable='0' then
if Q(1)='1' then
ACK_sig<='0';
Q:=(others=>'0');
else
Q:= Q + '1';
end if;
else
ACK_sig<='1';
end if;
end if;
end process;
SP_ACKn<=ACK_sig;
--------------------------------------------------------------------------addr part
--ADDR_LATCH(6 DOWNTO 0)<=ADR(6 DOWNTO 0);
--ADDR_LATCH(7)<=ADR(7);
--ADDR_LATCH(10 DOWNTO 8)<=CARDID_REG(2 downto 0);
ADDR_LATCH(10 DOWNTO 7)<=GPIO(3 downto 0);
--process(SP_CLK)
--begin
-- if RST_INn='0' then
-- CARDID_REG<=(others=>'0');
-- elsif rising_edge(SP_CLK) then
-- CARDID_REG<=CARDID;
-- end if;
--end process;
PROCESS(SP_ALEn)
BEGIN
IF SP_ALEn ='0' AND SP_ALEn'EVENT THEN
ADDR_LATCH(6 DOWNTO 0)<=SP_AD(7 DOWNTO 1);
END IF;
END PROCESS;
--PROCESS(SP_CP_A0)
--BEGIN
--IF SP_CP_A0='1' AND SP_CP_A0'EVENT THEN
--IF SP_ALEn='0' THEN
--ADDR_LATCH(7)<=SP_AD(0);
--END IF;
--END IF;
--END PROCESS;
-----------------------------------------------------------------------address output
AOI_A(9 DOWNTO 0)<=ADDR_LATCH(9 DOWNTO 0);
--------------------------------------------------------------------------cs part
process(SP_CLK)
begin
IF CSn_END='1' OR RST_INn='0' THEN
card_cs_reg<='1';
ELSIF SP_CLK'EVENT AND SP_CLK='1' THEN
if SP_CS1n='0' then
card_cs_reg<='0';
end if;
end if;
end process;
PROCESS(SP_OEn)
BEGIN
IF RST_INn='0' OR SP_ALEn='0' THEN
CSn_END<='0';
ELSIF SP_OEn='1' AND SP_OEn'EVENT THEN
CSn_END<='1';
END IF;
END PROCESS;
pm5352_cs_sig<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10)='0')
else '1';
idt82p2282_cs_sig<= '0' when ( card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="10")
else '1';
zi9001_1_cs_sig<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="11"
and ADDR_LATCH(8 downto 7)="00")
else '1';
zi9001_2_cs_sig<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="11"
and ADDR_LATCH(8 downto 7)="01")
else '1';
xr16c2850_csa_sig<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="11"
and ADDR_LATCH(8 downto 7)="10"
and ADDR_LATCH(6)='0')
else '1';
xr16c2850_csb_sig<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="11"
and ADDR_LATCH(8 downto 7)="10"
and ADDR_LATCH(6)='1')
else '1';
intternal_reg_cs<= '0' when (card_cs_reg='0'
and ADDR_LATCH(10 downto 9)="11"
and ADDR_LATCH(8 downto 7)="11")
else '1';
--intternal_reg_cs<= '1';
pm5352_cs<=pm5352_cs_sig;
idt82p2282_cs<=idt82p2282_cs_sig;
zi9001_1_cs<=zi9001_1_cs_sig;
zi9001_2_cs<=zi9001_2_cs_sig;
xr16c2850_csa<=xr16c2850_csa_sig;
xr16c2850_csb<=xr16c2850_csb_sig;
------------------------------------------------------------generate rd signal
process(RST_INn,SP_CLK)
begin
IF RST_INn='0' or SP_CS1n='1' THEN
rd_reg<='1';
elsif rising_edge(SP_CLK) then
if card_cs_reg='0' and SP_OEn='1' then
rd_reg<='0';
end if;
end if;
end process;
AOI_RD<=rd_reg;
---------------------------------------------------------------------generate wr signal
--process(RST_INn,SP_CLK)
--begin
--IF RST_INn='0' or SP_WR='1' THEN
-- wr_en<='1';
--elsif rising_edge(SP_CLK) then
-- if card_cs_reg='0' and SP_WR='0' then
-- wr_en<='0';
-- end if;
--end if;
--end process;
--
--
--process(RST_INn,SP_CLK)
--begin
--IF RST_INn='0' or SP_WR='1' THEN
-- wr_reg<='1';
--elsif rising_edge(SP_CLK) then
-- if card_cs_reg='0' and SP_WR='0' and wr_en='0' then
-- wr_reg<='0';
-- end if;
--end if;
--end process;
--process(RST_INn,SP_CLK)
--variable Q: std_logic_vector(1 downto 0);
--begin
--IF RST_INn='0' or SP_OEn='1' THEN
-- Q:=(others=>'0');
-- wr_en<='1';
--elsif rising_edge(SP_CLK) then
-- if card_cs_reg='0' and SP_RD='0' then
-- if Q(1)='1' then
-- Q:=(others=>'0');
-- wr_en<='0';
-- else
-- Q:= Q + '1';
-- end if;
-- else
-- wr_en<='1';
-- end if;
--end if;
--end process;
--process(RST_INn,SP_CLK)
--begin
--IF RST_INn='0' or SP_RD='1' THEN
-- wr_reg<='1';
--elsif rising_edge(SP_CLK) then
--
-- if card_cs_reg='0' and SP_WR='0' and wr_en='0' then
-- wr_reg<='0';
-- end if;
--end if;
--end process;
process(RST_INn,SP_CLK)
variable Q :std_logic_vector(2 downto 0);
begin
if RST_INn='0' or SP_WR='1' then
Q:=(others=>'0');
wr_reg<='1';
elsif rising_edge(SP_CLK) then
if SP_RD='0' then
if Q(2)='1' then
wr_reg<='0';
Q:=(others=>'0');
else
Q:= Q + '1';
end if;
else
wr_reg<='1';
end if;
end if;
end process;
AOI_WR<=wr_reg;
---------------------------------------------------------------------rd data part
--DATA_LATCH_EN<=NOT (AOI_READYn OR SP_DIR_A1);
--DATA_LATCH_EN<=SP_RD;
--
----PROCESS(DATA_LATCH_EN)
----BEGIN
----IF DATA_LATCH_EN='1' AND DATA_LATCH_EN'EVENT THEN
----AOI_DATA_LATCH(15 DOWNTO 8)<=AOI_D(15 DOWNTO 8);
----END IF;
----END PROCESS;
--
--PROCESS(DATA_LATCH_EN)
--BEGIN
--IF DATA_LATCH_EN='1' AND DATA_LATCH_EN'EVENT THEN
--AOI_DATA_LATCH(7 DOWNTO 0)<=AOI_D(7 DOWNTO 0);
--END IF;
--END PROCESS;
PROCESS(SP_OEn)
BEGIN
IF RST_INn='0' OR SP_CP_A0='1' THEN
SP_AD_OUT_EN1<='0';
ELSIF SP_OEn'EVENT AND SP_OEn='0' THEN
IF SP_DIR_A1='0' THEN
SP_AD_OUT_EN1<='1';
END IF;
END IF;
END PROCESS;
PROCESS(SP_CP_A0)
BEGIN
IF RST_INn='0' OR SP_OEn='1' THEN --SP_ALEn='0' THEN
SP_AD_OUT_EN0<='0';
ELSIF SP_CP_A0'EVENT AND SP_CP_A0='1' THEN
IF SP_DIR_A1='0' and SP_ALEn='1' THEN
SP_AD_OUT_EN0<='1';
END IF;
END IF;
END PROCESS;
SP_AD<= AOI_DATA_LATCH(7 DOWNTO 0) WHEN SP_AD_OUT_EN0='1' AND LOCAL_CSn='1' ELSE
"00000000" WHEN SP_AD_OUT_EN1='1' AND LOCAL_CSn='1' ELSE
"ZZZZZZZZ";
---------------------------------------------------------wr part
PROCESS(SP_ALEn)
BEGIN
IF RST_INn='0' OR CSn_END='1' THEN
SP_D_LOW_LATCH_EN<='0';
ELSIF SP_ALEn'EVENT AND SP_ALEn='1' THEN
IF SP_DIR_A1='1' THEN
SP_D_LOW_LATCH_EN<='1';
END IF;
END IF;
END PROCESS;
PROCESS(SP_CP_A0)
BEGIN
IF RST_INn='0' OR CSn_END='1' THEN
SP_D_HI_LATCH_EN<='0';
ELSIF SP_CP_A0'EVENT AND SP_CP_A0='1' THEN
IF SP_DIR_A1='1' AND SP_ALEn='1' THEN
SP_D_HI_LATCH_EN<='1';
END IF;
END IF;
END PROCESS;
PROCESS(SP_CLK)
BEGIN
IF SP_CLK'EVENT AND SP_CLK='0' THEN
SP_D_LATCH0<=SP_D_LOW_LATCH_EN;
END IF;
END PROCESS;
PROCESS(SP_CLK)
BEGIN
IF SP_CLK'EVENT AND SP_CLK='1' THEN
SP_D_LATCH1<=SP_D_HI_LATCH_EN;
END IF;
END PROCESS;
PROCESS(SP_D_LATCH0)
BEGIN
IF SP_D_LATCH0'EVENT AND SP_D_LATCH0='1' THEN
AOI_D_WR(7 DOWNTO 0)<=SP_AD(7 DOWNTO 0);
END IF;
END PROCESS;
PROCESS(SP_D_LATCH1)
BEGIN
IF SP_D_LATCH1'EVENT AND SP_D_LATCH1='1' THEN
AOI_D_WR(15 DOWNTO 8)<=SP_AD(7 DOWNTO 0);
END IF;
END PROCESS;
AOI_D(7 DOWNTO 0)<= AOI_D_WR(7 DOWNTO 0) WHEN (SP_D_LOW_LATCH_EN='1' and (pm5352_cs_sig='0' or idt82p2282_cs_sig='0'
or zi9001_1_cs_sig='0' or zi9001_2_cs_sig='0' or xr16c2850_csa_sig='0'
or xr16c2850_csb_sig='0') )
ELSE "ZZZZZZZZ";
---------------------------------------------------------------------read data bus and internal registers
process(RST_INn,SP_CLK)
begin
if RST_INn='0' then
AOI_DATA_LATCH(7 downto 0)<=(others=>'0');
elsif rising_edge(SP_CLK) then
if rd_reg='0' then
-- if (pm5352_cs_sig='0' or idt82p2282_cs_sig='0' or zi9001_1_cs_sig='0' or zi9001_2_cs_sig='0'
-- or xr16c2850_csa_sig='0' or xr16c2850_csb_sig='0') then
AOI_DATA_LATCH(7 downto 0)<=AOI_D(7 DOWNTO 0);
if intternal_reg_cs='0' then
-- AOI_DATA_LATCH(7 downto 0)<="10011010";
case ADDR_LATCH(6 downto 0) is
when "0000000" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RTS_DTE_reg;
when "0000001" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DTR_DTE_reg;
when "0000010" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RLPBK_DTE_reg;
when "0000011" => AOI_DATA_LATCH(7 downto 0)<="0000000" & LLPBK_DTE_reg;
when "0000100" => AOI_DATA_LATCH(7 downto 0)<="0000000" & CTS_DTE;
when "0000101" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DCD_DTE;
when "0000110" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DSR_DTE;
when "0000111" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RI_DTE;
when "0001000" => AOI_DATA_LATCH(7 downto 0)<="0000000" & CTS_DCE_reg;
when "0001001" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DCD_DCE_reg;
when "0001010" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DSR_DCE_reg;
when "0001011" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RI_DCE_reg;
when "0001100" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RTS_DCE;
when "0001101" => AOI_DATA_LATCH(7 downto 0)<="0000000" & DTR_DCE;
when "0001110" => AOI_DATA_LATCH(7 downto 0)<="0000000" & RLPBK_DCE;
when "0001111" => AOI_DATA_LATCH(7 downto 0)<="0000000" & LLPBK_DCE;
when "0010000" => AOI_DATA_LATCH(7 downto 0)<="0000000" & PM5352_RST_reg;
when "0010001" => AOI_DATA_LATCH(7 downto 0)<="0000000" & XR16C2850_RST_reg;
when "0010010" => AOI_DATA_LATCH(7 downto 0)<="0000000" & IDT82P2282_RST_reg;
when "0010011" => AOI_DATA_LATCH(7 downto 0)<="0000000" & Zi9001_RST1_reg;
when "0010100" => AOI_DATA_LATCH(7 downto 0)<="0000000" & Zi9001_RST2_reg;
when "0010101" => AOI_DATA_LATCH(7 downto 0)<= "00" & PM5352_INT & IDT82P2282_INT & XR16C2850_INTA
& XR16C2850_INTB & Zi9001_INT1 & Zi9001_INT2;
when others => null;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------write internal registers
process(RST_INn,wr_reg)
begin
if RST_INn='0' then
RTS_DTE_reg<='0';
DTR_DTE_reg<='0';
RLPBK_DTE_reg<='0';
LLPBK_DTE_reg<='0';
CTS_DCE_reg<='0';
DCD_DCE_reg<='0';
DSR_DCE_reg<='0';
RI_DCE_reg<='0';
PM5352_RST_reg<='1';
XR16C2850_RST_reg<='1';
IDT82P2282_RST_reg<='1';
Zi9001_RST1_reg<='1';
Zi9001_RST2_reg<='1';
elsif wr_reg'event and wr_reg='1' then
if intternal_reg_cs='0' then
case ADDR_LATCH(6 downto 0) is
when "0000000" => RTS_DTE_reg<=AOI_D_WR(0);
when "0000001" => DTR_DTE_reg<=AOI_D_WR(0);
when "0000010" => RLPBK_DTE_reg<=AOI_D_WR(0);
when "0000011" => LLPBK_DTE_reg<=AOI_D_WR(0);
when "0001000" => CTS_DCE_reg<=AOI_D_WR(0);
when "0001001" => DCD_DCE_reg<=AOI_D_WR(0);
when "0001010" => DSR_DCE_reg<=AOI_D_WR(0);
when "0001011" => RI_DCE_reg<=AOI_D_WR(0);
when "0010000" => PM5352_RST_reg<=AOI_D_WR(0);
when "0010001" => XR16C2850_RST_reg<=AOI_D_WR(0);
when "0010010" => IDT82P2282_RST_reg<=AOI_D_WR(0);
when "0010011" => Zi9001_RST1_reg<=AOI_D_WR(0);
when "0010100" => Zi9001_RST2_reg<=AOI_D_WR(0);
when others => null;
end case;
end if;
end if;
end process;
RTS_DTE<=RTS_DTE_reg;
DTR_DTE<=DTR_DTE_reg;
RLPBK_DTE<=RLPBK_DTE_reg;
LLPBK_DTE<=LLPBK_DTE_reg;
CTS_DCE<=CTS_DCE_reg;
DCD_DCE<=DCD_DCE_reg;
DSR_DCE<=DSR_DCE_reg;
RI_DCE<=RI_DCE_reg;
-- PM5352_RST<= PM5352_RST_reg;
PM5352_RST<='1';
-- XR16C2850_RST<= not (XR16C2850_RST_reg);
XR16C2850_RST<='0';
-- Zi9001_RST1<= Zi9001_RST1_reg;
Zi9001_RST1<='1';
-- Zi9001_RST2<= Zi9001_RST2_reg;
Zi9001_RST2<='1';
-- IDT82P2282_RST<= IDT82P2282_RST_reg;
IDT82P2282_RST<='1';
--
-- ADD_INT<=PM5352_INT and (not XR16C2850_INTA) and (not XR16C2850_INTB)
-- and Zi9001_INT1 and Zi9001_INT2 and IDT82P2282_INT;
-----------------------------------------------------------------------
process(RST_INn,clk_2M)
begin
if RST_INn='0' then
counter<=(others=>'0');
elsif rising_edge(clk_2M) then
counter<=counter + 1;
end if;
end process;
process(clk_2M)
begin
if rising_edge(clk_2M) then
if counter(4)='0' then
clk_64k<='0';
else
clk_64k<='1';
end if;
end if;
end process;
-- process(RST_INn,counter)
-- begin
-- if RST_INn='0' then
-- clk_64K_reg<='0';
-- elsif counter="000000" then
-- clk_64K_reg<='1';
-- elsif counter="100000" then
-- clk_64K_reg<='0';
-- end if;
-- end process;
clk_out<=clk_64k;
process(RST_INn,clk_64k)
begin
if RST_INn='0' then
sta<=A;
elsif clk_64k'event and clk_64k='0' then
case sta is
when A => data_v35<='1';
sta<=B;
when B => data_v35<='1';
sta<=C;
when C => data_v35<='0';
sta<=D;
when D => data_v35<='0';
sta<=E;
when E => data_v35<='1';
sta<=F;
when F => data_v35<='1';
sta<=G;
when G => data_v35<='1';
sta<=H;
when H => data_v35<='0';
sta<=A;
when others => null;
end case;
end if;
end process;
end Behavioral;
楼主请将问题细化，要不一大堆代码谁看谁晕。原来要做什么？现在想要加什么？ 分析得出的结论在哪里？疑问在哪里？
答案是怎么被问出来的？
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