SAM L10/L11 Family
Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone,
Crypto, and Enhanced PTC
Features
•
•
Operating Conditions:
1.62V to 3.63V, -40ºC to +125ºC, DC to 32 MHz
Core:
32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm
®
Cortex
®
-M23 with:
– Single-cycle hardware multiplier
– Hardware divider
– Nested Vector Interrupt Controller (NVIC)
– Memory Protection Unit (MPU)
– Stack Limit Checking
– TrustZone
®
for ARMv8-M (optional)
System
– Power-on Reset (POR) and programmable Brown-out Detection (BOD)
– 8-channel Direct Memory Access Controller (DMAC)
– 8-channel event system for Inter-peripheral Core-independent Operation
– CRC-32 generator
Memory
– 16/32/64-KB Flash
– 4/8/16-KB SRAM
– 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
– 256 bytes TrustRAM with physical protection features
Clock Management
– Flexible clock distribution optimized for low power
– 32.768 kHz crystal oscillator
– 32.768 kHz ultra low-power internal RC oscillator
– 0.4 to 32 MHz crystal oscillator
– 16/12/8/4 MHz low-power internal RC oscillator
– Ultra low-power digital Frequency-Locked Loop (DFLLULP)
– 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
– One frequency meter
Low-Power and Power Management
– Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
• Active mode (< 25 μA/MHz)
• Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time
• Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
• Off mode (< 100 nA)
– Static and dynamic power gating architecture
– Sleepwalking peripherals
– Two performance levels
•
•
•
•
©
2020 Microchip Technology Inc.
Datasheet
DS60001513F-page 1
SAM L10/L11 Family
– Embedded Buck/LDO regulator with on-the-fly selection
•
Security
– Up to four tamper pins for static and dynamic intrusion detections
– Data Flash
• Optimized for secure storage
• Address and data scrambling with user-defined key (optional)
• Rapid tamper erase on scrambling key and on one user-defined row
• Silent access for data read noise reduction
– TrustRAM
• Address and data scrambling with user-defined key
• Chip-level tamper detection on physical RAM to resist microprobing attacks
• Rapid tamper erase on scrambling key and RAM data
• Silent access for data read noise reduction
• Data remanence prevention
– Peripherals
• One True Random Generator (TRNG)
• AES-128, SHA-256, and GCM cryptography accelerators (optional)
• Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external
devices from the non-secure application (optional)
– TrustZone for flexible hardware isolation of memories and peripherals (optional)
• Up to six regions for the Flash
• Up to two regions for the Data Flash
• Up to two regions for the SRAM
• Individual security attribution for each peripheral, I/O, external interrupt line, and Event System
Channel
– Secure Boot with SHA-based authentication (optional)
– Up to three debug access levels
– Up to three Chip Erase commands to erase part of or the entire embedded memories
– Unique 128-bit serial number
– SAM L11 Securely Key Provisioned (KPH) (optional)
• Key Provisioning using Root of Trust flow
• Security Software Framework using Kinibi-M
™
Software Development Kit (SDK)
•
Advanced Analog and Touch
– One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
– Two Analog Comparators (AC) with window compare function
– One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
– Three Operational Amplifiers (OPAMP)
– One enhanced Peripheral Touch Controller (PTC):
• Up to 20 self-capacitance channels
• Up to 100 (10x10) mutual-capacitance channels
• Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
• Hardware noise filtering and noise signal desynchronization for high conducted immunity
• Driven Shield Plus for better noise immunity and moisture tolerance
• Parallel Acquisition through Polarity control
• Supports wake-up on touch from Standby Sleep mode
Communication Interfaces
– Up to three Serial Communication Interfaces (SERCOM) that can operate as:
• USART with full-duplex and single-wire half-duplex configuration
•
©
2020 Microchip Technology Inc.
Datasheet
DS60001513F-page 2
SAM L10/L11 Family
•
•
•
•
•
•
I
2
C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the
second instance
Serial Peripheral Interface (SPI)
ISO7816 on one instance (Available on 32-pin packages only)
RS-485 on one instance (Available on 32-pin packages only)
LIN Slave on one instance (Available on 32-pin packages only)
Timers/Output Compare/Input Capture
– Three 16-bit Timers/Counters (TC), each configurable as:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
– 32-bit Real-Time Counter (RTC) with clock/calendar functions
– Watchdog Timer (WDT) with Window mode
Input/Output (I/O)
– Up to 25 programmable I/O lines
– Eight external interrupts (EIC)
– One non-maskable interrupt (NMI)
– One Configurable Custom Logic (CCL) that supports:
• Combinatorial logic functions, such as AND, NAND, OR, and NOR
• Sequential logic functions, such as Flip-Flop and Latches
Qualification and Class-B Support
– AEC-Q100 Grade 1 (-40ºC to +125ºC)
– Class-B safety library, IEC 60730 (future)
Debugger Development Support
– Two-pin Serial Wire Debug (SWD) programming and debugging interface
Packages
(1)
VQFN
24
17
0.5 mm
4x4x0.9 mm
32
25
0.5 mm
5x5x1 mm
5x5x0.9 mm(2)
TQFP
32
25
0.8 mm
7x7x1 mm
SSOP
24
17
0.65 mm
8.2x5.3x2.0 mm
WLCSP
32
25
0.4 mm
2.79x2.79x0.482 mm
•
•
•
•
Type
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
Notes:
1. AEC-Q100 Grade 1 Qualification is only offered for VQFN (with wettable flanks) and TQFP devices.
2. VQFN with wettable flanks.
©
2020 Microchip Technology Inc.
Datasheet
DS60001513F-page 3
SAM L10/L11 Family
Table of Contents
Features......................................................................................................................................................... 1
1.
2.
3.
4.
Configuration Summary........................................................................................................................ 14
Ordering Information............................................................................................................................. 16
Block Diagram.......................................................................................................................................17
Pinouts.................................................................................................................................................. 18
4.1.
4.2.
4.3.
4.4.
5.
6.
Multiplexed Signals.................................................................................................................... 19
Oscillators Pinout....................................................................................................................... 20
Serial Wire Debug Interface Pinout............................................................................................ 21
General Purpose I/O (GPIO) Clusters........................................................................................21
Signal Descriptions List ........................................................................................................................22
Power Considerations........................................................................................................................... 24
6.1.
6.2.
6.3.
6.4.
6.5.
Power Supplies.......................................................................................................................... 24
Power Supply Constraints.......................................................................................................... 24
Power-On Reset and Brown-Out Detectors............................................................................... 25
Voltage Regulators..................................................................................................................... 25
Typical Powering Schematic...................................................................................................... 25
7.
Analog Peripherals Considerations.......................................................................................................27
7.1.
7.2.
Reference Voltages.................................................................................................................... 28
Analog On Demand Feature...................................................................................................... 28
8.
Device Startup.......................................................................................................................................29
8.1.
8.2.
8.3.
8.4.
Clocks Startup............................................................................................................................ 29
Initial Instructions Fetching.........................................................................................................29
I/O Pins.......................................................................................................................................29
Performance Level Overview..................................................................................................... 29
9.
Product Mapping................................................................................................................................... 30
10. Memories.............................................................................................................................................. 32
10.1. Embedded Memories................................................................................................................. 32
10.2. NVM Rows................................................................................................................................. 34
10.3. Serial Number............................................................................................................................ 40
11. Processor and Architecture...................................................................................................................41
11.1.
11.2.
11.3.
11.4.
Cortex-M23 Processor............................................................................................................... 41
Nested Vector Interrupt Controller..............................................................................................43
High-Speed Bus System............................................................................................................ 46
SRAM Quality of Service............................................................................................................48
12. Peripherals Configuration Summary..................................................................................................... 50
13. SAM L11 Specific Security Features..................................................................................................... 53
13.1. Features..................................................................................................................................... 53
©
2020 Microchip Technology Inc.
Datasheet
DS60001513F-page 4
SAM L10/L11 Family
13.2.
13.3.
13.4.
13.5.
13.6.
Arm TrustZone Technology for Armv8-M....................................................................................53
Crypto Acceleration.................................................................................................................... 63
Secure Boot................................................................................................................................66
Secure Pin Multiplexing on SERCOM........................................................................................ 66
Data Flash Scrambling............................................................................................................... 66
14. Boot ROM............................................................................................................................................. 67
14.1.
14.2.
14.3.
14.4.
Features..................................................................................................................................... 67
Block Diagram............................................................................................................................ 67
Product Dependencies............................................................................................................... 68
Functional Description................................................................................................................68
15. PAC - Peripheral Access Controller...................................................................................................... 89
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
15.7.
Overview.................................................................................................................................... 89
Features..................................................................................................................................... 89
Block Diagram............................................................................................................................ 89
Product Dependencies............................................................................................................... 89
Functional Description................................................................................................................90
Register Summary......................................................................................................................94
Register Description................................................................................................................... 95
16. Device Service Unit (DSU).................................................................................................................. 115
16.1. Overview...................................................................................................................................115
16.2. Features................................................................................................................................... 115
16.3. Block Diagram.......................................................................................................................... 116
16.4. Signal Description.....................................................................................................................116
16.5. Product Dependencies............................................................................................................. 116
16.6. Debug Operation...................................................................................................................... 117
16.7. Programming............................................................................................................................ 119
16.8. Security Enforcement............................................................................................................... 120
16.9. Device Identification................................................................................................................. 122
16.10. Functional Description..............................................................................................................123
16.11. Register Summary....................................................................................................................128
16.12. Register Description.................................................................................................................129
17. Clock System...................................................................................................................................... 156
17.1.
17.2.
17.3.
17.4.
17.5.
17.6.
17.7.
Clock Distribution..................................................................................................................... 156
Synchronous and Asynchronous Clocks..................................................................................157
Register Synchronization......................................................................................................... 157
Enabling a Peripheral............................................................................................................... 160
On Demand Clock Requests....................................................................................................160
Power Consumption vs. Speed................................................................................................ 160
Clocks after Reset.................................................................................................................... 161
18. GCLK - Generic Clock Controller........................................................................................................ 162
18.1.
18.2.
18.3.
18.4.
Overview.................................................................................................................................. 162
Features................................................................................................................................... 162
Block Diagram.......................................................................................................................... 162
Signal Description.................................................................................................................... 163
©
2020 Microchip Technology Inc.
Datasheet
DS60001513F-page 5
