STM32L4P5xx
Ultra-low-power Arm
®
Cortex
®
-M4 32-bit MCU+FPU, 150 DMIPS,
up to 1-MB Flash memory, 320-KB SRAM, LCD-TFT, ext. SMPS
Datasheet
-
production data
Features
Includes ST state-of-the-art patented
technology
Ultra-low-power with FlexPowerControl
•
1.71 V to 3.6 V power supply
•
-40 °C to 85/125 °C temperature range
•
Batch acquisition mode (BAM)
•
150 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
•
22 nA Shutdown mode (5 wakeup pins)
•
42 nA Standby mode (5 wakeup pins)
•
190 nA Standby mode with RTC
•
2.95
μA
Stop 2 with RTC
•
110
μA/MHz
Run mode (LDO mode)
•
41
μA/MHz
Run mode (@ 3.3 V SMPS mode)
•
5 µs wakeup from Stop mode
•
Brownout reset (BOR) in all modes except
Shutdown
UFQFPN48
(7 x 7 mm)
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP100 (14 x 14 mm)
LQFP144 (20 x 20 mm)
UFBGA132 (7 x 7 mm)
UFBGA169 (7 x 7 mm) WLCSP100
(pitch 0.4 mm)
•
2 x Octo-SPI memory interfaces
General-purpose inputs/outputs
•
Up to 136 fast I/Os, most 5 V-tolerant, up to 14
I/Os with independent supply down to 1.08 V
Performance benchmark
•
1.25 DMIPS/MHz (Drystone 2.1)
•
409.20 CoreMark
®
(3.41 CoreMark/MHz @120
MHz)
Energy benchmark
•
285 ULPMark™CP score
Core
•
Arm
®
32-bit Cortex
®
-M4 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 120 MHz,
MPU, 150 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
Up to 24 capacitive sensing channels
•
Support touchkey, linear and rotary touch
sensors
Clock management
•
4 to 48 MHz crystal oscillator
•
32 kHz crystal oscillator for RTC (LSE)
•
Internal 16 MHz factory-trimmed RC (±1%)
•
Internal low-power 32 kHz RC (±5%)
•
Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
•
Internal 48 MHz with clock recovery
•
3 PLLs for system clock, USB, audio, ADC
Memories
•
1-Mbyte Flash memory, 2 banks read-while-
write, proprietary code readout protection
•
320 Kbytes of SRAM including 64 Kbytes with
hardware parity check
•
External memory interface for static memories
supporting SRAM, PSRAM, NOR, NAND and
FRAM memories
March 2021
This is information on a product in full production.
DS12903 Rev 3
1/311
www.st.com
STM32L4P5xx
Interconnect matrix
•
1 AHB bus matrix
Advanced graphics features
•
Chrom-ART Accelerator (DMA2D) for
enhanced graphic content creation
•
LCD-TFT controller
14-channel DMA controller
23 communication peripherals
•
USB OTG 2.0 full-speed, LPM and BCD
•
2x SAIs (serial audio interface)
•
4x I2C FM+(1 Mbit/s), SMBus/PMBus
•
6x USARTs (ISO 7816, LIN, IrDA, modem)
•
3x SPIs (5x SPIs with the dual Octo-SPI)
•
CAN (2.0B Active) and 2x SDMMC
•
8- to 14-bit camera interface up to 32 MHz
(black and white) or 10 MHz (color)
•
8-/16-bit parallel synchronous data
input/output slave interface (PSSI)
16x timers and watchdog
•
2 x 16-bit advanced motor-control
•
2 x 32-bit general purpose timers
•
5 x 16-bit general purpose timers
•
2x 16-bit basic timers
•
2x low-power 16-bit timers (available in Stop
mode)
•
2x watchdogs
•
1x SysTick timer
•
RTC with hardware calendar, alarms and
calibration
11 analog peripherals (independent
supply)
•
2x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
•
2x 12-bit DAC, low-power sample and hold
•
2x operational amplifiers with built-in PGA
•
2x ultra-low-power comparators
•
2x digital filters for sigma delta modulator
•
1x temperature sensor
True random generator
CRC calculation unit
HASH (SHA-256) hardware accelerator
Debug mode
•
Serial wire debug (SWD)
•
JTAG
•
Embedded Trace Macrocell
™
(ETM)
96-bit unique ID
Table 1. Device summary
Reference
STM32L4P5xx
Part numbers
STM32L4P5AE, STM32L4P5AG, STM32L4P5CE, STM32L4P5CG, STM32L4P5QE,
STM32L4P5QG, STM32L4P5RE, STM32L4P5RG, STM32L4P5VE, STM32L4P5VG,
STM32L4P5ZE, STM32L4P5ZG
2/311
DS12903 Rev 3
STM32L4P5xx
Contents
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
Arm
®
Cortex
®
-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 19
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
3.4.2
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
3.6
3.7
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
Peripheral and interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.16.1
3.16.2
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 43
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 44
3.17
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 44
DS12903 Rev 3
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Contents
STM32L4P5xx
3.18
3.19
3.20
3.21
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 44
Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Octo-SPI IO manager (OCTOSPIIOM) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.21.1
3.21.2
3.21.3
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 50
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LCD-TFT controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 53
HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.33.1
3.33.2
3.33.3
3.33.4
3.33.5
3.33.6
3.33.7
Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 55
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.34
3.35
3.36
3.37
3.38
3.39
3.40
3.41
4/311
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 57
Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Universal synchronous/asynchronous receiver transmitter (USART) . . . 59
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 60
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 61
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DS12903 Rev 3
STM32L4P5xx
Contents
3.42
3.43
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 63
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.43.1
3.43.2
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 63
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 140
Embedded reset and power control block characteristics . . . . . . . . . . 140
Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 189
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Extended interrupt and event controller input (EXTI) characteristics . . 208
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