2SJ518
Silicon P Channel MOS FET
REJ03G0875-0400
(Previous: ADE-208-580B)
Rev.4.00
Sep 07, 2005
Description
High speed power switching
Features
•
Low on-resistance
R
DS (on)
= 0.35
Ω
typ. (at V
GS
= –10 V, I
D
= –1 A)
•
Low drive current
•
4 V gate drive devices
•
High speed switching
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK
R
)
D
3
2
1
G
4
1. Gate
2. Drain
3. Source
4. Drain
S
Note: Marking is “AZ”.
*UPAK is a trademark of Renesas Technology Corp.
Rev.4.00 Sep 07, 2005 page 1 of 6
2SJ518
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body to drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel temperature
Symbol
V
DSS
V
GSS
I
D
I
D (pulse)
I
DR
Note 1
Value
–60
±20
–2
–4
–2
–2
0.34
1
150
Unit
V
V
A
A
A
A
mJ
W
°C
°C
I
AP
E
AR
Note 2
Pch
Tch
Note 3
Storage temperature
Tstg
–55 to +150
Notes: 1. PW
≤
10
µs,
duty cycle
≤
1%
2. Value at Tch = 25°C, Rg
≥
50
Ω
3. Value at when using the aluminum ceramic board (12.5
×
20
×
0.7 mm)
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source breakdown voltage
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Static drain to source on state resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body to drain diode forward voltage
Body to drain diode reverse recovery time
Note:
4. Pulse test
Symbol
V
(BR) DSS
V
(BR) GSS
I
DSS
I
GSS
V
GS (off)
R
DS (on)
R
DS (on)
|y
fs
|
Ciss
Coss
Crss
t
d (on)
t
r
t
d (off)
t
f
V
DF
t
rr
Min
–60
±20
—
—
–1.0
—
—
1.2
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
0.35
0.45
2.0
220
110
35
10
11
45
30
–1.05
50
Max
—
—
–10
±10
–2.0
0.46
0.63
—
—
—
—
—
—
—
—
—
—
Unit
V
V
µA
µA
V
Ω
Ω
S
pF
pF
pF
ns
ns
ns
ns
V
ns
Test Conditions
I
D
= –10 mA, V
GS
= 0
I
G
=
±100 µA,
V
DS
= 0
V
DS
= –60 V, V
GS
= 0
V
GS
=
±16
V, V
DS
= 0
I
D
= –1 mA, V
DS
= –10 V
Note 4
I
D
= –1 A, V
GS
= –10 V
I
D
= –1 A, V
GS
= –4 V
Note 4
I
D
= –1 A, V
DS
= –10 V
V
DS
= –10 V
V
GS
= 0
f = 1 MHz
V
GS
= –10 V
I
D
= –1 A
R
L
= 30
Ω
I
F
= –2 A, V
GS
= 0
I
F
= –2 A, V
GS
= 0
di
F
/dt = 50 A/µs
Note 4
Rev.4.00 Sep 07, 2005 page 2 of 6
2SJ518
Main Characteristics
Power vs. Temperature Derating
2.0
Maximum Safe Operation Area
–100
–30
Pch (W)
I
D
(A)
Test Condition:
When using the aluminum ceramic
board (12.5
×
20
×
70 mm)
1.5
–10
–3
–1
–0.3
–0.1
–0.03
PW
100
µs
s
=
10
(1
DC
sh ms
Op
ot)
er
at
ion
1m
Channel Dissipation
1.0
Drain Current
0.5
Operation in
this area is
limited by R
DS (on)
0
0
50
100
150
200
Ta = 25°C
–0.01
–1
–0.1 –0.3
–3
–10
–30
–100
Ambient Temperature
Ta (°C)
Drain to Source Voltage V
DS
(V)
Typical Output Characteristics
–5
–10 V –6 V
Pulse Test
–5 V
–5
Typical Transfer Characteristics
V
DS
= –10 V
Pulse Test
I
D
(A)
Drain Current
I
D
(A)
–4
–4 V
–3
–3.5 V
–4
–3
Drain Current
–2
–3 V
–1
V
GS
= –2.5 V
–2
25°C
–25°C
–1
Tc = 75°C
0
0
–2
–4
–6
–8
–10
0
0
–1
–2
–3
–4
–5
Drain to Source Voltage
V
DS
(V)
Gate to Source Voltage
V
GS
(V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source on State Resistance
R
DS (on)
(Ω)
Drain to Source Saturation Voltage
V
DS (on)
(V)
–5
Pulse Test
Static Drain to Source on State Resistance
vs. Drain Current
10
Pulse Test
5
–4
2
1
0.5
V
GS
= –4 V
–10 V
0.2
0.1
–0.1 –0.2
–3
–2
–1
–0.5 A
I
D
= –2 A
–1 A
0
0
–4
–8
–12
–16
–20
–0.5
–1
–2
–5
–10
Gate to Source Voltage
V
GS
(V)
Drain Current
I
D
(A)
Rev.4.00 Sep 07, 2005 page 3 of 6
2SJ518
Static Drain to Source on State Resistance
vs. Temperature
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
1.0
Pulse Test
0.8
I
D
= –2 A
0.6
V
GS
= –4 V
–0.5 A, –1 A
10
5
Tc = –25°C
2
25°C
1
75°C
0.5
0.4
–0.5 A, –1 A
0.2
–10 V
–2 A
0.2
0.1
–0.1
V
DS
= –10 V
Pulse Test
–0.2
–0.5
–1
–2
–5
–10
0
–40
0
40
80
120
160
Case Temperature
Tc (°C)
Drain Current I
D
(A)
Typical Capacitance vs.
Drain to Source Voltage
1000
300
100
30
Crss
10
3
1
Body-Drain Diode Reverse
Recovery Time
100
Reverse Recovery Time trr (ns)
50
Capacitance C (pF)
Ciss
Coss
20
di / dt = 50 A /
µs
V
GS
= 0, Ta = 25°C
10
–0.1 –0.2
–0.5
–1
–2
–5
–10
V
GS
= 0
f = 1 MHz
0
–10
–20
–30
–40
–50
Reverse Drain Current
I
DR
(A)
Drain to Source Voltage V
DS
(V)
Dynamic Input Characteristics
Switching Characteristics
V
DS
(V)
–20
–4
Switching Time t (ns)
V
DD
= –10 V
–25 V
–50 V
V
GS
(V)
0
0
100
50
td(off)
tf
td(on)
tr
Drain to Source Voltage
Gate to Source Voltage
–40
V
DS
V
GS
–60
V
DD
= –10 V
–25 V
–50 V
–8
20
10
5
–12
–80
I
D
= –2 A
0
4
8
12
16
–16
2
1
–0.1 –0.2
–100
–20
20
V
GS
= –10 V, V
DD
= –30 V
Ta = 25°C, duty
≤
1 %
–0.5
–1
–2
–5
–10
Gate Charge
Qg (nc)
Drain Current
I
D
(A)
Rev.4.00 Sep 07, 2005 page 4 of 6
2SJ518
Reverse Drain Current vs.
Source to Drain Voltage
–5
Maximum Avalanche Energy vs.
Channel Temperature Derating
Repetitive Avalanche Energy E
AR
(mJ)
0.5
I
AP
= –2 A
V
DD
= –25 V
duty < 0.1 %
Rg
≥
50
Ω
Reverse Drain Current I
DR
(A)
–4
0.4
–3
–5 V
–10 V
V
GS
= 0, 5 V
0.3
–2
0.2
–1
Pulse Test
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
0.1
0
25
50
75
100
125
150
Source to Drain Voltage
V
SD
(V)
Channel Temperature Tch (°C)
Avalanche Test Circuit
Avalanche Waveform
1
• L • I
AP2
•
2
V
DSS
V
DSS
– V
DD
V
(BR)DSS
I
AP
V
DD
I
D
V
DS
V
DS
Monitor
L
I
AP
Monitor
E
AR
=
Rg
D.U.T
Vin
–15 V
50
Ω
V
DD
0
Switching Time Test Circuit
Vin
Vin Monitor
D.U.T.
R
L
Vout
Monitor
10%
Waveform
90%
90%
90%
Vin
–10 V
50
Ω
V
DD
= –30 V
Vout
td(on)
10%
tr
td(off)
10%
tf
Rev.4.00 Sep 07, 2005 page 5 of 6
模拟电子
