3N165, 3N166
MONOLITHIC DUAL P-CHANNEL
Linear Integrated Systems
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
(T
A
= 25°C unless otherwise noted)
Drain-Source or Drain-Gate Voltage
(NOTE 2)
3N165
3N166
Transient G-S Voltage
(NOTE 3)
Gate-Gate Voltage
Drain Current
(NOTE 2)
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation (One Side)
Total Derating above 25°C
40 V
30 V
±125
V
±80
V
50 mA
-65°C to +200°C
-55°C to +150°C
+300°C
300 mW
4.2 mW/°C
ENHANCEMENT MODE
MOSFET
1
7
C
G1
G2
D2
S
3
5
D1
8 4
Device Schematic
TO-99
Bottom View
ELECTRICAL CHARACTERISTICS (T
A
=25
°
C and V
BS
=0 unless otherwise specified)
SYMBOL
I
GSSR
I
GSSF
I
DSS
I
SDS
I
D(on)
V
GS(th)
V
GS(th)
r
DS(on)
g
fs
g
os
C
iss
C
rss
C
oss
R
E
(Y
fs
)
CHARACTERISTICS
Gate Reverse Leakage Current
Gate Forward Leakage Current
Drain to Source Leakage Current
Source to Drain Leakage Current
On Drain Current
Gate Source Threshold Voltage
Gate Source Threshold Voltage
Drain Source ON Resistance
Forward Transconductance
Output Admittance
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
LIMITS
MIN. MAX.
--
--
--
--
--
-5
-2
-2
--
1500
--
--
--
--
10
-10
-25
-200
-400
-30
-5
-5
300
3000
300
3.0
0.7
3.0
--
µs
pF
V
DS
= -15V
(NOTE 4)
V
DS
= -15V
(NOTE 4)
I
D
= -10mA
f=100MHz
I
D
= -10mA
f=1MHz
mA
V
V
ohms
µs
µs
pA
UNITS
V
GS
= 40 V
V
GS
= -40 V
T
A
=+125°C
V
DS
= -20 V
V
SD
= -20 V
V
DS
= -15 V
V
DS
= -15 V
V
DS
= V
GS
V
GS
= -20 V
V
DS
= -15V
V
DB
= 0
V
GS
= -10 V
I
D
= -10
µA
I
D
= -10
µA
I
D
= -100
µA
I
D
= -10mA
f=1kHz
CONDITIONS
Common Source Forward Transconductance
1200
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
MATCHING CHARACTERISTICS 3N165
SYMBOL
Y
fs1
/Y
fs2
V
GS1-2
CHARACTERISTICS
Forward Transconductance Ratio
Gate Source Threshold Voltage Differential
Change with Temperature
LIMITS
MIN. MAX.
0.90
--
--
1.0
100
100
mV
µV/°C
UNITS
V
DS
= -15 V
V
DS
= -15 V
V
DS
= -15 V
CONDITIONS
I
D
= -500
µA
I
D
= -500
µA
I
A
= -500
µA
f=1kHz
∆V
GS1-2
/∆T Gate Source Threshold Voltage Differential
T
A
= -55°C to = +25°C
TYPICAL SWITCHING WAVEFORM
V
DD
10%
10%
R
1
R
2
50
Ω
INPUT PULSE
Rise Time
≤
2ns
Pulse Width
≥
200ns
Switching Times Test Circuit
V
OUT
t
on
t
r
90%
10%
t
off
10%
SAMPLING SCOPE
T
r
≤
0.2ns
C
IN
≤
2pF
R
IN
≥
10M
Switching Times Test Circuit
NOTES:
1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static
charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures:
To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when
being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove
devices from circuits with the power on, as transient voltages may cause permanant damage to the devices.
2. Per transistor.
3. Devices must mot be tested at
±125V
more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261
FPGA/CPLD
