54AC139
•
54ACT139 Dual 1-of-4 Decoder/Demultiplexer
August 1998
54AC139
•
54ACT139
Dual 1-of-4 Decoder/Demultiplexer
General Description
The ’AC/’ACT139 is a high-speed, dual 1-of-4 decoder/
demultiplexer. The device has two independent decoders,
each accepting two inputs and providing four
mutually-exclusive active-LOW outputs. Each decoder has
an active-LOW Enable input which can be used as a data in-
put for a 4-output demultiplexer. Each half of the ’AC/
’ACT139 can be used as a function generator providing all
four minterms of two variables.
n
n
n
n
n
n
Multifunction capability
Two completely independent 1-of-4 decoders
Active LOW mutually exclusive outputs
Outputs source/sink 24 mA
’ACT139 has TTL-compatible inputs
Standard Military Drawing (SMD)
— ’AC139: 5962-87623
— ’ACT139: 5962-87553
Features
n
I
CC
reduced by 50%
Logic Symbols
IEEE/IEC
DS100269-8
DS100269-2
Pin Names
A
0
, A
1
E
O
0
–O
3
Description
Address Inputs
Enable Inputs
Outputs
DS100269-1
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100269
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
can be used as the data input for a 4-output demultiplexer
application. Each half of the ’AC/’ACT139 generates all four
minterms of two variables. These four minterms are useful in
some applications, replacing multiple gate functions as
shown in , and thereby reducing the number of packages re-
quired in a logic network.
DS100269-3
Pin Assignment
for LCC
DS100269-6
FIGURE 1. Gate Functions (Each Half)
Truth Table
Inputs
DS100269-4
Outputs
A
1
X
L
L
H
H
O
0
H
L
H
H
H
O
1
H
H
L
H
H
O
2
H
H
H
L
H
O
3
H
H
H
H
L
E
H
L
L
L
L
A
0
X
L
H
L
H
Functional Description
The ’AC/’ACT139 is a high-speed dual 1-of-4 decoder/
demultiplexer. The device has two independent decoders,
each of which accepts two binary weighted inputs (A
0
–A
1
)
and provides four mutually exclusive active-LOW outputs
(O
0
–O
3
). Each decoder has an active-LOW enable (E).
When E is HIGH all outputs are forced HIGH. The enable
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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2
Logic Diagram
DS100269-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’AC
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54AC/ACT
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
125 mV/ns
±
50 mA
±
50 mA
−65˚C to +150˚C
175˚C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol
Parameter
V
CC
(V)
54AC
T
A
=
−55˚C to
+125˚C
Guaranteed
Limits
V
IH
Minimum High Level
Input Voltage
V
IL
Maximum Low Level
Input Voltage
V
OH
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
(Note 2)
V
IN
= V
IL
or V
IH
I
OH
= −12 mA
V
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
V
I
OUT
= −50 µA
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
Units
Conditions
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
V
3.0
4.5
5.5
I
IN
Maximum Input
Leakage Current
5.5
0.50
0.50
0.50
V
µA
(Note 2)
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
±
1.0
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4
DC Characteristics for ’AC Family Devices
Symbol
Parameter
V
CC
(V)
(Continued)
54AC
T
A
=
−55˚C to
+125˚C
Guaranteed
Limits
Units
Conditions
I
OLD
I
OHD
I
CC
(Note 3)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
50
−50
80.0
mA
mA
µA
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54AC
@
25˚C is identical to 74AC
@
25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
54ACT
T
A
=
−55˚C to
+125˚C
Guaranteed
Limits
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
(Note 5)
V
IN
= V
IL
or V
IH
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
(Note 5)
V
IN
= V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
Units
Conditions
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
V
V
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I
CC
/Input
(Note 6)
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 7:
I
CC
for 54ACT
@
25˚C is identical to 74ACT
@
25˚C.
0.50
0.50
V
µA
mA
mA
mA
µA
5.5
5.5
5.5
5.5
5.5
±
1.0
1.6
50
−50
80.0
5
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