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5962R9676602QYX

256X8 MULTI-PORT SRAM, CDFP42, FP-42

器件类别：存储   

厂商名称：Renesas(瑞萨电子)

厂商官网：https://www.renesas.com/

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参数 预览 参数对比
器件参数
参数名称
属性值
厂商名称
Renesas(瑞萨电子)
零件包装代码
DFP
包装说明
DFP,
针数
42
Reach Compliance Code
unknown
ECCN代码
3A001.A.2.C
Is Samacsys
N
最长访问时间
500 ns
JESD-30 代码
R-XDFP-F42
JESD-609代码
e4
长度
26.925 mm
内存密度
2048 bit
内存集成电路类型
MULTI-PORT SRAM
内存宽度
8
功能数量
1
端子数量
42
字数
256 words
字数代码
256
工作模式
ASYNCHRONOUS
最高工作温度
125 °C
最低工作温度
-55 °C
组织
256X8
封装主体材料
UNSPECIFIED
封装代码
DFP
封装形状
RECTANGULAR
封装形式
FLATPACK
并行/串行
PARALLEL
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class Q
座面最大高度
2.54 mm
最大供电电压 (Vsup)
5.25 V
最小供电电压 (Vsup)
4.75 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
MILITARY
端子面层
GOLD
端子形式
FLAT
端子节距
1.27 mm
端子位置
DUAL
总剂量
100k Rad(Si) V
宽度
16.255 mm
Base Number Matches
1
文档预览
HS-81C55RH, HS-81C56RH
TM
Data Sheet
August 2000
File Number
3039.2
Radiation Hardened 256 x 8 CMOS RAM
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96766. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-96766
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . .>1 x 10
8
rad(Si)/s
- Latch-Up Free . . . . . . . . . . . . . . . . . . >1 x 10
12
rad(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9676601QXC
5962R9676601QYC
5962R9676601VXC
5962R9676601VYC
5962R9676602QXC
5962R9676602QYC
5962R9676602VXC
5962R9676602VYC
INTERNAL
MKT. NUMBER
HS1-81C55RH-8
HS9-81C55RH-8
HS1-81C55RH-Q
HS9-81C55RH-Q
HS1-81C56RH-8
HS9-81C56RH-8
HS1-81C56RH-Q
HS9-81C56RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Functional Diagram
IO/M
AD0 - AD7
CE OR CE
†
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
TIMER
C
PORT C
8
PC0 - PC5
VDD (10V)
GND
256 x 8
STATIC
RAM
A
PORT A
8
PA0 - PA7
PORT B
B
8
PB0 - PB7
†
81C55RH = CE
81C56RH = CE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HS-81C55RH, HS-81C56RH
Pinouts
40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PC3
PC4
TIMER IN
RESET
PC5
TIMER OUT
IO / M
CE or CE
†
1
2
3
4
5
6
7
8
40 VDD
39 PC2
38 PC1
37 PC0
36 PB7
35 PB6
34 PB5
33 PB4
32 PB3
31 PB2
30 PB1
29 PB0
28 PA7
27 PA6
26 PA5
25 PA4
24 PA3
23 PA2
22 PA1
21 PA0
PC3
PC4
TIMER IN
RESET
PC5
TIMER OUT
IO/M
CE OR CE
RD
WR
ALE
AD0
AD1
AD2
AD3
NC
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA7
PA6
PA5
NC
PA4
PA3
PA2
PA1
PA0
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INTERSIL OUTLINE K42.A
TOP VIEW
RD 9
WR 10
ALE 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
†
81C55RH = CE
81C56RH = CE
2
HS-81C55RH, HS-81C56RH
Pin Descriptions
SYMBOL
RESET
TYPE
I
NAME AND FUNCTION
Reset:
Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT).
Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET
pulse should typically be two HS-80C85RH clock cycle times.
Address/Data:
Three-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The
8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of
ALE. The address can be either for the memory section or the I/O section depending on the IO/M input. The
8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal.
Chip Enable:
On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE
and is ACTIVE HIGH.
Read Control:
Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/M pin
is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or
command/status registers will be read to the AD bus.
Write Control:
Input low on this line with the Chip Enable active causes the data on the Address/Data bus to
be written to the RAM or I/O ports and command/status register, depending on IO/M.
Address Latch Enable:
This control signal latches both the address on the AD0 - AD7 lines and the state of
the Chip Enable and IO/M into the chip at the falling edge of ALE.
I/O Memory:
Selects memory if low and I/O and command/status registers if high.
Port A:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port B:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port C:
These 6 pins can function as either input port, output port, or as control signals for PA and PB.
Programming is done through the command register. When PC0 - PC5 are used as control signals, they will
provide the following:
PC0 - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 - B STB (Port B Strobe)
Timer Input:
Input to the counter-timer.
Timer Output:
This output can be either a square wave or a pulse, depending on the timer mode.
Voltage:
+5V.
Ground:
Ground reference.
AD0 - AD7
I/O
CE or CE
RD
I
I
WR
ALE
IO/M
PA0 - PA7 (8)
PB0 - PB7 (8)
PC0 - PC7 (8)
I
I
I
I/O
I/O
I/O
TIMER IN
TIMER OUT
VDD
GND
I
O
I
I
3
HS-81C55RH, HS-81C56RH
Waveforms
READ
CE (81C55RH)
OR
CE (81C56RH)
IO/M
tAD
AD
0-7
tAL
ALE
tLL
RD
tLC
tCC
tRV
tRIDE
tRD
tCL
tRDF
ADDRESS
tLA
DATA VALID
WRITE
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD
0-7
tAL
ALE
tLL
WR
ADDRESS
tLA
tDW
DATA VALID
tCL
tLC
tCL
tCC
tWD
tRV
4
HS-81C55RH, HS-81C56RH
Waveforms
(Continued)
STROBED INPUT
BF
tSBF
STROBED
tSS
INTR
tRDI
tSI
tRBE
RD
tPSS
INPUT DATA
FROM PORT
tPHS
STROBED OUTPUT
BF
tSBE
STROBE
tWBF
INTR
tWI
WR
tWP
OUTPUT DATA
TO PORT
tSI
5
查看更多>
参数对比
与5962R9676602QYX相近的元器件有：5962R9676602VYX、5962R9676602VXX、5962R9676601QXX、5962R9676601VXX、5962R9676602QXX、5962R9676601QYX、5962R9676601VYX、5962-01-363-9538。描述及对比如下：
型号 5962R9676602QYX 5962R9676602VYX 5962R9676602VXX 5962R9676601QXX 5962R9676601VXX 5962R9676602QXX 5962R9676601QYX 5962R9676601VYX 5962-01-363-9538
描述 256X8 MULTI-PORT SRAM, CDFP42, FP-42 256X8 MULTI-PORT SRAM, CDFP42, FP-42 256X8 MULTI-PORT SRAM, CDIP40, CERAMIC, DIP-40 256X8 MULTI-PORT SRAM, CDIP40, CERAMIC, DIP-40 256X8 MULTI-PORT SRAM, CDIP40, CERAMIC, DIP-40 256X8 MULTI-PORT SRAM, CDIP40, CERAMIC, DIP-40 256X8 MULTI-PORT SRAM, CDFP42, FP-42 256X8 MULTI-PORT SRAM, CDFP42, FP-42 5962-01-363-9538
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子) Renesas(瑞萨电子)
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown not_compliant
JESD-30 代码 R-XDFP-F42 R-XDFP-F42 R-CDIP-T40 R-CDIP-T40 R-CDIP-T40 R-CDIP-T40 R-XDFP-F42 R-XDFP-F42 R-XDIP-T40
端子数量 42 42 40 40 40 40 42 42 40
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
封装主体材料 UNSPECIFIED UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED UNSPECIFIED UNSPECIFIED CERAMIC
封装代码 DFP DFP DIP DIP DIP DIP DFP DFP DIP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK FLATPACK IN-LINE IN-LINE IN-LINE IN-LINE FLATPACK FLATPACK IN-LINE
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class Q MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class Q MIL-PRF-38535 Class V MIL-PRF-38535 Class Q MIL-PRF-38535 Class Q MIL-PRF-38535 Class V 38535Q/M;38534H;883B
表面贴装 YES YES NO NO NO NO YES YES NO
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子形式 FLAT FLAT THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE FLAT FLAT THROUGH-HOLE
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
零件包装代码 DFP DFP DIP DIP DIP DIP DFP DFP -
包装说明 DFP, DFP, DIP, DIP, DIP, DIP, DFP, DFP, -
针数 42 42 40 40 40 40 42 42 -
ECCN代码 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C -
最长访问时间 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns 500 ns -
JESD-609代码 e4 e4 e4 e4 e4 e4 e4 e4 -
内存密度 2048 bit 2048 bit 2048 bit 2048 bit 2048 bit 2048 bit 2048 bit 2048 bit -
内存集成电路类型 MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM -
内存宽度 8 8 8 8 8 8 8 8 -
功能数量 1 1 1 1 1 1 1 1 -
字数 256 words 256 words 256 words 256 words 256 words 256 words 256 words 256 words -
字数代码 256 256 256 256 256 256 256 256 -
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS -
组织 256X8 256X8 256X8 256X8 256X8 256X8 256X8 256X8 -
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL -
最大供电电压 (Vsup) 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V -
最小供电电压 (Vsup) 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V -
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V -
端子面层 GOLD GOLD GOLD GOLD GOLD GOLD GOLD GOLD -
端子节距 1.27 mm 1.27 mm - - - - 1.27 mm 1.27 mm 2.54 mm
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V -
Base Number Matches 1 1 1 1 1 1 1 - -
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器件捷径:
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
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