71M6543F/71M6543G
Energy Meter ICs
GENERAL DESCRIPTION
The 71M6543F/71M6543G are 4th-generation polyphase metering
systems-on-chips (SoCs) with a 5MHz 8051-compatible MPU core,
low-power real-time clock (RTC) with digital temperature
compensation, flash memory, and LCD driver. Our Single
Converter Technology® with a 22-bit delta-sigma ADC, seven
analog inputs, digital metrology temperature compensation,
precision voltage reference, and a 32-bit computation engine (CE)
supports a wide range of metering applications with very few
external components.
The 71M6543F/71M6543G support optional interfaces to the
71M6xx3 series of isolated sensors that offer BOM cost reduction,
immunity to magnetic tamper, and enhanced reliability. The ICs
feature ultra-low-power operation in active and battery modes, 5KB
shared RAM, and 64KB (71M6543F) or 128KB (71M6543G) of
flash memory, which can be programmed with code and/or data
during meter operation.
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
C
NEUTRAL
B
A
FEATURES
•
0.1% Typical Accuracy Over 2000:1 Current
Range
•
Exceeds IEC 62053/ANSI C12.20 Standards
•
Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
•
Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
•
High-Speed Wh/VARh Pulse Outputs with
Programmable Width
•
64KB Flash, 5KB RAM (71M6543F)
•
128KB Flash, 5KB RAM (71M6543G)
•
Up to Four Pulse Outputs with Pulse Co
unt
•
Four-Quadrant Metering, Phase Sequencing
•
Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
•
Independent 32-Bit Compute Engine
•
46-64Hz Line Frequency Range with the Same
Calibration
•
Phase Compensation (±7°)
•
Three Battery-Backup Modes:
Brownout Mode
LCD Mode
Sleep Mode
•
Wake-Up on Pin Events and Wake-on-Timer
•
1µA in Sleep Mode
•
Flash Security
•
In-System Program Update
•
8-Bit MPU (80515), Up to 5MIPS
•
Full-Speed MPU Clock in Brownout Mode
•
LCD Driver:
6 Common Segment Drivers
Up to 56 Selectable Pins
•
Up to 51 Multifunction DIO Pins
•
Hardware Watchdog Timer (WDT)
•
I
2
C/MICROWIRE® EEPROM Interface
•
SPI Interface with Flash Program Capability
•
Two UARTs for IR and AMR
•
IR LED Driver with Modulation
•
Industrial Temperature Range
•
100-Pin Lead-Free LQFP Package
Shunt Current Sensors
LOAD
POWER SUPPLY
NEUTRAL
71M6xx3
71M6xx3
71M6xx3
Note: This system is referenced to Neutral
3x 71M6xx3
Resistor Dividers
Pulse Transformers
VADC10 (VC)
IADC6
IADC7
}
IC
VADC9 (VB)
IADC4
IADC5
}
IB
VADC8 (VA)
IADC2
IADC3
}
IA
VREF
MUX and ADC
IADC0
IADC1
}
IN*
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6543F/
71M6543G
TEMPERATURE
SENSOR
WAKE-UP
REGULATOR
VBAT
VBAT_RTC
BATTERY
MONITOR
RTC
BATTERY
BATTERY
RAM
COMPUTE
ENGINE
FLASH
MEMORY
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
SERIAL PORTS
LCD DISPLAY
AMR
TX
RX
MODUL- RX
ATOR
TX
POWER FAULT
COMPARATOR
8888.8888
PULSES,
DIO
I
2
C or µWire
EEPROM
32 kHz
IR
RTC
TIMERS
ICE
MPU
HOST
V3P3D
OSCILLATOR/
PLL
XIN
XOUT
9/17/2010
SPI INTERFACE
*IN = Neutral Current
Single Converter Technology is a registered trademark of Maxim Integrated
Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-5375; Rev 2; 10/13
71M6543F/71M6543G Data Sheet
Table of Contents
1
2
Introduction ....................................................................................................................................... 10
Hardware Description ....................................................................................................................... 11
2.1 Hardware Overview ................................................................................................................... 11
2.2 Analog Front-End (AFE) ............................................................................................................ 12
2.2.1 Signal Input Pins ............................................................................................................ 13
2.2.2 Input Multiplexer............................................................................................................. 14
2.2.3 Delay Compensation ..................................................................................................... 19
2.2.4 ADC Pre-Amplifier ......................................................................................................... 20
2.2.5 A/D Converter (ADC) ..................................................................................................... 20
2.2.6 FIR Filter ........................................................................................................................ 20
2.2.7 Voltage References ....................................................................................................... 20
2.2.8 71M6xx3 Isolated Sensor Interface ............................................................................... 22
2.3 Digital Computation Engine (CE) ............................................................................................... 25
2.3.1 CE Program Memory ..................................................................................................... 25
2.3.2 CE Data Memory ........................................................................................................... 25
2.3.3 CE Communication with the MPU ................................................................................. 25
2.3.4 Meter Equations ............................................................................................................. 26
2.3.5 Real-Time Monitor (RTM) .............................................................................................. 26
2.3.6 Pulse Generators ........................................................................................................... 26
2.3.7 CE Functional Overview ................................................................................................ 28
2.4 80515 MPU Core ....................................................................................................................... 30
2.4.1 Memory Organization and Addressing .......................................................................... 30
2.4.2 Special Function Registers (SFRs)................................................................................ 32
2.4.3 Generic 80515 Special Function Registers ................................................................... 33
2.4.4 Instruction Set ................................................................................................................ 35
2.4.5 UARTs ........................................................................................................................... 35
2.4.6 Timers and Counters ..................................................................................................... 38
2.4.7 WD Timer (Software Watchdog Timer) ......................................................................... 39
2.4.8 Interrupts ........................................................................................................................ 39
2.5 On-Chip Resources ................................................................................................................... 46
2.5.1 Physical Memory............................................................................................................ 46
2.5.2 Oscillator ........................................................................................................................ 48
2.5.3 PLL and Internal Clocks................................................................................................. 49
2.5.4 Real-Time Clock (RTC) ................................................................................................. 49
2.5.5 71M6543 Temperature Sensor ...................................................................................... 53
2.5.6 71M6xx3 Temperature Sensor ...................................................................................... 56
2.5.7 71M6543 Battery Monitor .............................................................................................. 56
2.5.8 71M6xx3 VCC Monitor ................................................................................................... 56
2.5.9 UART and Optical Interface ........................................................................................... 56
2.5.10 Digital I/O and LCD Segment Drivers ............................................................................ 57
2.5.11 EEPROM Interface ........................................................................................................ 65
2.5.12 SPI Slave Port................................................................................................................ 67
2.5.13 Hardware Watchdog Timer ............................................................................................ 71
2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins) ............................................................. 72
Functional Description ..................................................................................................................... 74
3.1 Theory of Operation ................................................................................................................... 74
3.2 Battery Modes ............................................................................................................................ 74
3.2.1 BRN Mode ..................................................................................................................... 77
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71M6543F/71M6543G Data Sheet
3.2.2 LCD Mode ...................................................................................................................... 77
3.2.3 SLP Mode ...................................................................................................................... 78
3.3 Fault and Reset Behavior .......................................................................................................... 79
3.3.1 Events at Power-Down .................................................................................................. 79
3.3.2 IC Behavior at Low Battery Voltage ............................................................................... 80
3.3.3 Reset Sequence ............................................................................................................ 80
3.3.4 Watchdog Timer (WDT) Reset ...................................................................................... 80
3.4 Wake-Up Behavior ..................................................................................................................... 81
3.4.1 Wake on Hardware Events ............................................................................................ 81
3.4.2 Wake on Timer............................................................................................................... 83
3.5 Data Flow and MPU/CE Communication ................................................................................... 83
Application Information .................................................................................................................... 85
4.1 Connecting 5 V Devices............................................................................................................. 85
4.2 Directly Connected Sensors ...................................................................................................... 85
4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts ............................................... 86
4.4 System Using Current Transformers ......................................................................................... 87
4.5 Metrology Temperature Compensation ..................................................................................... 88
4.5.1 Temperature Compensation .......................................................................................... 88
4.5.2 Temperature Coefficients for the 71M6543F and 71M6543G ....................................... 88
4.5.3 Temperature Coefficients for the 71M6xx3 ................................................................... 89
4.5.4 Temperature Compensation for VREF and Shunt Sensors .......................................... 89
4.5.5 Temperature Compensation of VREF and Current Transformers................................. 90
2
4.6 Connecting I C EEPROMs ........................................................................................................ 92
4.7 Connecting Three-Wire EEPROMs ........................................................................................... 92
4.8 UART0 (TX/RX) ......................................................................................................................... 92
4.9 Optical Interface (UART1).......................................................................................................... 93
4.10 Connecting the Reset Pin .......................................................................................................... 93
4.11 Connecting the Emulator Port Pins ............................................................................................ 94
4.12 Flash Programming.................................................................................................................... 94
4.12.1 Flash Programming via the ICE Port ............................................................................. 94
4.12.2 Flash Programming via the SPI Port ............................................................................. 94
4.13 MPU Demonstration Code ......................................................................................................... 94
4.14 Crystal Oscillator ........................................................................................................................ 95
4.15 Meter Calibration ........................................................................................................................ 95
Firmware Interface ............................................................................................................................ 96
5.1 I/O RAM Map –Functional Order ............................................................................................... 96
5.2 I/O RAM Map – Alphabetical Order ......................................................................................... 102
5.3 CE Interface Description .......................................................................................................... 116
5.3.1 CE Program ................................................................................................................. 116
5.3.2 CE Data Format ........................................................................................................... 116
5.3.3 Constants ..................................................................................................................... 116
5.3.4 Environment ................................................................................................................. 117
5.3.5 CE Calculations ........................................................................................................... 117
5.3.6 CE Front-End Data (Raw Data) ................................................................................... 118
5.3.7 CE Status and Control ................................................................................................. 119
5.3.8 CE Transfer Variables ................................................................................................. 121
5.3.9 Pulse Generation ......................................................................................................... 123
5.3.10 CE Calibration Parameters .......................................................................................... 127
5.3.11 CE Flow Diagrams ....................................................................................................... 128
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71M6543F/71M6543G Data Sheet
6
71M6543 Specifications.................................................................................................................. 130
6.1 Absolute Maximum Ratings ..................................................................................................... 130
6.2 Recommended External Components ..................................................................................... 131
6.3 Recommended Operating Conditions ...................................................................................... 131
6.4 Performance Specifications ..................................................................................................... 132
6.4.1 Input Logic Levels ........................................................................................................ 132
6.4.2 Output Logic Levels ..................................................................................................... 132
6.4.3 Battery Monitor............................................................................................................. 133
6.4.4 Temperature Monitor ................................................................................................... 134
6.4.5 Supply Current ............................................................................................................. 135
6.4.6 V3P3D Switch .............................................................................................................. 136
6.4.7 Internal Power Fault Comparators ............................................................................... 136
6.4.8 2.5 V Voltage Regulator – System Power ................................................................... 136
6.4.9 2.5 V Voltage Regulator – Battery Power .................................................................... 137
6.4.10 Crystal Oscillator .......................................................................................................... 137
6.4.11 Phase-Locked Loop (PLL) ........................................................................................... 137
6.4.12 LCD Drivers ................................................................................................................. 137
6.4.13 VLCD Generator .......................................................................................................... 138
6.4.14 71M6543 VREF ........................................................................................................... 140
6.4.15 ADC Converter............................................................................................................. 141
6.4.16 Pre-Amplifier for IADC0-IADC1 ................................................................................... 142
6.5 Timing Specifications ............................................................................................................... 143
6.5.1 Flash Memory .............................................................................................................. 143
6.5.2 SPI Slave ..................................................................................................................... 143
6.5.3 EEPROM Interface ...................................................................................................... 143
6.5.4 RESET Pin ................................................................................................................... 144
6.5.5 Real-Time Clock (RTC) ............................................................................................... 144
6.6 100-Pin LQFP Package Outline Drawing ................................................................................ 145
6.7 71M6543 Pinout ....................................................................................................................... 146
6.8 71M6543 Pin Descriptions ....................................................................................................... 147
6.8.1 71M6543 Power and Ground Pins .............................................................................. 147
6.8.2 71M6543 Analog Pins .................................................................................................. 148
6.8.3 71M6543 Digital Pins ................................................................................................... 149
6.8.4 I/O Equivalent Circuits ................................................................................................. 151
7
Ordering Information ...................................................................................................................... 152
7.1 71M6543 Ordering Guide ........................................................................................................ 152
8
Related Information ..................................................................................................................... 152
9
Contact Information ..................................................................................................................... 152
Appendix A: Acronyms .......................................................................................................................... 153
Appendix B: Revision History................................................................................................................ 154
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71M6543F/71M6543G Data Sheet
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 9
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ......................................................... 12
Figure 3. AFE Block Diagram (Four CTs) ................................................................................................... 13
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) ..................................................................... 17
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) ..................................................................... 17
Figure 6: General Topology of a Chopped Amplifier .................................................................................. 21
Figure 7: CROSS Signal with
CHOP_E
= 00 ............................................................................................... 21
Figure 8: RTM Timing ................................................................................................................................. 26
Figure 9. Pulse Generator FIFO Timing...................................................................................................... 28
Figure 10: Samples from Multiplexer Cycle (Frame) .................................................................................. 29
Figure 11: Accumulation Interval ................................................................................................................ 29
Figure 12: Interrupt Structure ...................................................................................................................... 45
Figure 13: Automatic Temperature Compensation ..................................................................................... 52
Figure 14: Optical Interface ......................................................................................................................... 57
Figure 15: Optical Interface (UART1) ......................................................................................................... 57
Figure 16: Connecting an External Load to DIO Pins ................................................................................. 59
Figure 17: LCD Waveforms......................................................................................................................... 64
Figure 18: 3-wire Interface. Write Command, HiZ=0. ................................................................................ 66
Figure 19: 3-wire Interface. Write Command, HiZ=1 ................................................................................. 67
Figure 20: 3-wire Interface. Read Command. ............................................................................................ 67
Figure 21: 3-Wire Interface. Write Command when CNT=0 ...................................................................... 67
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................... 67
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations ................................................ 69
Figure 24: Voltage, Current, Momentary and Accumulated Energy ........................................................... 74
Figure 25: Operation Modes State Diagram ............................................................................................... 75
Figure 26: MPU/CE Data Flow .................................................................................................................... 84
Figure 27: Resistive Voltage Divider (Voltage Sensing) ............................................................................. 85
Figure 28. CT with Single-Ended Input Connection (Current Sensing) ...................................................... 85
Figure 29: CT with Differential Input Connection (Current Sensing) .......................................................... 85
Figure 30: Differential Resistive Shunt Connections (Current Sensing) ..................................................... 85
Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor .............................................. 86
Figure 32. System Using Current Transformers ......................................................................................... 87
2
Figure 33: I C EEPROM Connection .......................................................................................................... 92
Figure 34: Connections for UART0 ............................................................................................................. 92
Figure 35: Connection for Optical Components .......................................................................................... 93
Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ........ 94
Figure 37: External Components for the Emulator Interface ...................................................................... 94
Figure 38: CE Data Flow: Multiplexer and ADC........................................................................................ 128
Figure 39: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase ......................... 128
Figure 40: CE Data Flow: Squaring and Summation Stages .................................................................... 129
Figure 41: 100-pin LQFP Package Outline ............................................................................................... 145
Figure 42: Pinout for the LQFP-100 Package ........................................................................................... 146
Figure 43: I/O Equivalent Circuits ............................................................................................................. 151
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