INTEGRATED CIRCUITS
DATA SHEET
74AHC273; 74AHCT273
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
File under Integrated Circuits, IC06
1999 Sep 01
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FEATURES
•
Ideal buffer for MOS microcontroller or memory
•
Common clock and master reset
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt trigger actions
•
Inputs accepts voltages higher than V
CC
•
See ‘377’ for clock enable version
•
See ‘373’ for transparent latch version
•
See ‘374’ for 3-state version
•
For AHC only: operates with CMOS input levels
•
For AHCT only: operates with TTL input levels
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
DESCRIPTION
74AHC273; 74AHCT273
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
CP to Q
n
MR to Q
n
f
max
C
I
C
O
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
4.2
3.7
120
3.0
4.0
14.0
4.0
3.9
120
3.0
4.0
18.0
ns
ns
MHz
pF
pF
pF
AHCT
UNIT
1999 Sep 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
MR
reset (clear)
load ‘1’
load ‘0’
Note
1. H = HIGH voltage level;
L
H
H
CP
X
↑
↑
74AHC273; 74AHCT273
OUTPUTS
D
n
X
h
l
Q
n
L
L
L
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
↑
= LOW-to-HIGH transition.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC273D
74AHC273PW
74AHCT273D
74AHCT273PW
PINNING
PIN
1
MR
2, 5, 6, 9, 12, 15, 16 and 19 Q
0
to Q
7
3, 4, 7, 8, 13, 14, 17 and 18 D
0
to D
7
10
11
20
GND
CP
V
CC
SYMBOL
flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH; edge-triggered)
DC supply voltage
DESCRIPTION
master reset input (active LOW)
PACKAGES
NORTH AMERICA
PINS
74AHC273D
74AHC273PW DH
74AHCT273D
7AHCT273PW DH
20
20
20
20
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
1999 Sep 01
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
handbook, halfpage
MR 1
Q0 2
D0 3
D1 4
Q1 5
20 VCC
19 Q7
18 D7
17 D6
16 Q6
handbook, halfpage
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
273
Q2 6
D2 7
D3 8
Q3 9
GND 10
MNA459
15 Q5
14 D5
13 D4
12 Q4
11 CP
MNA460
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
11
1
C1
R
handbook, halfpage
3
4
2
5
6
9
12
15
16
19
MNA461
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
Q0
Q1
Q2
Q3
2
5
6
9
3
4
7
8
13
14
17
18
1D
7
8
13
14
17
18
Q4 12
Q5 15
Q6 16
Q7 19
1 MR
11 CP
MNA462
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 01
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74AHC273; 74AHCT273
D0
handbook, full pagewidth
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF1
RD
CP
MR
CP
FF2
RD
CP
FF3
RD
CP
FF4
RD
CP
FF5
RD
CP
FF6
RD
CP
FF7
RD
CP
FF8
RD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
MNA463
Q7
Fig.5 Logic diagram.
1999 Sep 01
5
