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74HC112N

HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16

器件类别：逻辑    逻辑   

厂商名称：Philips Semiconductors (NXP Semiconductors N.V.)

厂商官网：https://www.nxp.com/

器件标准：

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Philips Semiconductors (NXP Semiconductors N.V.)
包装说明
DIP, DIP16,.3
Reach Compliance Code
unknow
JESD-30 代码
R-PDIP-T16
JESD-609代码
e4
负载电容（CL）
50 pF
逻辑集成电路类型
J-K FLIP-FLOP
最大频率@ Nom-Su
20000000 Hz
最大I（ol）
0.004 A
功能数量
2
端子数量
16
最高工作温度
125 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP16,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
电源
2/6 V
认证状态
Not Qualified
表面贴装
NO
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
触发器类型
NEGATIVE EDGE
文档预览
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jun 10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FEATURES
•
Asynchronous set and reset
•
Output capability: standard
•
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nS
D
) and reset (nR
D
) inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT112
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
15
18
66
3.5
27
19
15
19
70
3.5
30
ns
ns
ns
MHz
pF
pF
HCT
UNIT
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
ORDERING INFORMATION
TYPE
NUMBER
74HC112D;
74HCT112D
74HC112DB;
74HCT112DB
74HC112N;
74HCT112N
74HC112PW;
74HCT112PW
PACKAGE
NAME
SO16
SSOP16
DIP16
TSSOP16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT112
VERSION
SOT109-1
SOT338-1
SOT38-1
SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil); long body
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 11
4, 10
5, 9
6, 7
8
15, 14
16
SYMBOL
1CP, 2CP
1K, 2K
1J, 2J
1S
D
, 2S
D
1Q, 2Q
1Q, 2Q
GND
1R
D
, 2R
D
V
CC
NAME AND FUNCTION
clock input (HIGH-to-LOW, edge triggered)
data inputs; flip-flops 1 and 2
data inputs; flip-flops 1 and 2
set inputs (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
reset inputs (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
FUNCTION TABLE
INPUTS
OPERATING MODE
nS
D
asynchronous set
asynchronous reset
undetermined
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Note
L
H
L
H
H
H
H
nR
D
H
L
L
H
H
H
H
nCP
X
X
X
↓
↓
↓
↓
nJ
X
X
X
h
l
h
l
74HC/HCT112
OUTPUTS
nK
X
X
X
h
h
l
l
nQ
H
L
H
q
L
H
q
nQ
L
H
L
q
H
L
q
Fig.4 Functional diagram.
1. If nS
D
and nR
D
simultaneously go from LOW to HIGH, the output states will
be unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition
X = don’t care
↓
= HIGH-to-LOW CP transition
Fig.5 Logic diagram (one flip-flop).
1998 Jun 10
4
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
74HC/HCT112
1998 Jun 10
5
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参数对比
与74HC112N相近的元器件有：74HC112、74HC112DB、74HC112PW、74HCT112DB、74HCT112、74HCT112N、74HCT112D、74HCT112PW。描述及对比如下：
型号 74HC112N 74HC112 74HC112DB 74HC112PW 74HCT112DB 74HCT112 74HCT112N 74HCT112D 74HCT112PW
描述 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 8-Line To 3-Line Priority Encoders 16-SO -40 to 85 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
是否Rohs认证 符合 - 符合 符合 符合 - 符合 符合 符合
厂商名称 Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) - Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.) Philips Semiconductors (NXP Semiconductors N.V.)
包装说明 DIP, DIP16,.3 - SSOP, SSOP16,.3 TSSOP, TSSOP16,.25 SSOP, SSOP16,.3 - DIP, DIP16,.3 SOP, SOP16,.25 TSSOP, TSSOP16,.25
Reach Compliance Code unknow - unknow unknow unknow - unknow unknow unknow
JESD-30 代码 R-PDIP-T16 - R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 - R-PDIP-T16 R-PDSO-G16 R-PDSO-G16
负载电容（CL） 50 pF - 50 pF 50 pF 50 pF - 50 pF 50 pF 50 pF
逻辑集成电路类型 J-K FLIP-FLOP - J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP - J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
最大频率@ Nom-Su 20000000 Hz - 20000000 Hz 20000000 Hz 20000000 Hz - 20000000 Hz 20000000 Hz 20000000 Hz
最大I（ol） 0.004 A - 0.004 A 0.004 A 0.004 A - 0.004 A 0.004 A 0.004 A
功能数量 2 2 2 2 2 - 2 2 2
端子数量 16 16 16 16 16 - 16 16 16
最高工作温度 125 °C - 125 °C 125 °C 85 °C - 85 °C 85 °C 85 °C
最低工作温度 -40 °C - -40 °C -40 °C -40 °C - -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 DIP - SSOP TSSOP SSOP - DIP SOP TSSOP
封装等效代码 DIP16,.3 - SSOP16,.3 TSSOP16,.25 SSOP16,.3 - DIP16,.3 SOP16,.25 TSSOP16,.25
封装形状 RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE - SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH - IN-LINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源 2/6 V - 2/6 V 2/6 V 5 V - 5 V 5 V 5 V
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified - Not Qualified Not Qualified Not Qualified
表面贴装 NO YES YES YES YES - NO YES YES
技术 CMOS - CMOS CMOS CMOS - CMOS CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE INDUSTRIAL - INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子形式 THROUGH-HOLE GULL WING GULL WING GULL WING GULL WING - THROUGH-HOLE GULL WING GULL WING
端子节距 2.54 mm - 0.635 mm 0.635 mm 0.635 mm - 2.54 mm 1.27 mm 0.635 mm
端子位置 DUAL DUAL DUAL DUAL DUAL - DUAL DUAL DUAL
触发器类型 NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE - NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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