INTEGRATED CIRCUITS
74LVC02A
Quad 2-input NOR gate
Product specification
Supersedes data of 1997 Aug 11
IC24 Data Handbook
1998 Apr 28
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
FEATURES
•
Wide supply range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
5-volt tolerant inputs, for interfacing with 5-volt logic
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nA, nB to nY
Input capacitance
Power dissipation capacitance per gate
DESCRIPTION
The 74LVC02A is a high performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC02A provides the 2-input NOR function.
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
Notes 1 and 2
TYPICAL
2.8
5.0
28
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC02A D
74LVC02A DB
74LVC02A PW
NORTH AMERICA
74LVC02A D
74LVC02A DB
74LVC02APW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4Y
4B
4A
3Y
3B
3A
PIN DESCRIPTION
PIN
NUMBER
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9, 12
7
14
SYMBOL
1Y – 4Y
1A – 4A
1B – 4B
GND
V
CC
Data inputs
Ground (0 V)
Positive supply voltage
NAME AND FUNCTION
Data outputs
SV00389
1998 Apr 28
2
853-2019 19310
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
LOGIC SYMBOL
LOGIC DIAGRAM (ONE GATE)
A
Y
2Y
3Y
4Y
4
10
13
B
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
1Y
1
SV00820
FUNCTION TABLE
INPUTS
OUTPUTS
nB
L
H
L
H
nY
H
L
L
L
nA
SV00390
LOGIC SYMBOL (IEEE/IEC)
2
3
5
6
8
9
11
12
≥1
1
L
L
H
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
≥1
4
≥1
10
≥1
13
SV00391
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC Input voltage range
DC output voltage range
Operating ambient temperature range in free-air
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
MIN
2.7
1.2
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
+85
20
10
V
V
V
V
°C
ns/V
UNIT
1998 Apr 28
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
ABSOLUTE MAXIMUM RATINGS
1
Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage (for max. speed
performance)
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
"50
–0.5 to V
CC
+ 0.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –18mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
CC
∆I
CC
Input leakage current
Quiescent supply current
Additional quiescent supply current
per input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
"0
1
"0.1
0.1
5
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*0.8
0.40
0.20
0.55
"5
10
500
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP
1
MAX
V
UNIT
V
IL
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1998 Apr 28
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±0.3V
MIN
t
PHL
/t
PLH
Propagation delay
nA, nB to nY
Figures 1, 2
1.5
TYP
1
2.8
MAX
4.6
MIN
1.5
V
CC
= 2.7V
TYP
1
3.2
MAX
5.6
V
CC
= 1.2V
TYP
11
ns
UNIT
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
w
2.7 V
V
M
= 0.5
S
V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
nA, nB, INPUT
V
M
TEST CIRCUIT
V
CC
S
1
2
<
V
CC
Open
GND
PULSE
GENERATOR
V
I
D.U.T.
R
T
V
O
500Ω
C
L
50pF
500Ω
GND
t
PHL
V
OH
nY OUTPUT
V
M
t
PLH
V
CC
t
2.7V
2.7V – 3.6V
V
I
V
CC
2.7V
Test
t
PLH
/t
PHL
S
1
Open
SY00077
SV00392
V
OL
Waveform 2.
Load circuitry for switching times.
Waveform 1. Input (nA, nB) to output (nY) propagation delays.
1998 Apr 28
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