A67L06181/A67L93361
Preliminary
Document Title
1M X 18, 512K X 36 LVTTL, Flow-through ZeBL
TM
SRAM
Revision History
Rev. No.
0.0
1M X 18, 512K X 36 LVTTL, Flow-through ZeBL
TM
SRAM
History
Initial issue
Issue Date
August, 20, 2005
Remark
Preliminary
PRELIMINARY
(August, 2005, Version 0.0)
AMIC Technology, Corp.
A67L06181/A67L93361
Preliminary
Features
Fast access time: 6.5/7.5/8.5 ns
(153, 133, 117 MHz)
Zero Bus Latency between READ and WRITE cycles
allows 100% bus utilization
Signal +3.3V
±
5% power supply
Individual Byte Write control capability
Clock enable (
CEN
) pin to enable clock and suspend
operations
Clock-controlled and registered address, data and
control signals
Registered output for pipelined applications
Three separate chip enables allow wide range of options
for CE control, address pipelining
Internally self-timed write cycle
Selectable BURST mode (Linear or Interleaved)
SLEEP mode (ZZ pin) provided
Available in 100 pin LQFP package
1M X 18, 512K X 36 LVTTL, Flow-through ZeBL
TM
SRAM
General Description
The AMIC Zero Bus Latency (ZeBL
TM
) SRAM family
employs high-speed, low-power CMOS designs using an
advanced CMOS process.
The A67L06181, A67L93361 SRAMs integrate a 1M X 18,
512K X 36 SRAM core with advanced synchronous
peripheral circuitry and a 2-bit burst counter. These SRAMs
are optimized for 100 percent bus utilization without the
insertion of any wait cycles during Write-Read alternation.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. The synchronous inputs include all address, all
data inputs, active low chip enable (
CE
), two additional chip
enables for easy depth expansion (CE2,
CE2
), cycle start
input (ADV/
LD
), synchronous clock enable (
CEN
), byte
write enables (
BW1
,
BW2
,
BW3
,
BW4
) and read/write
(R/
W
).
Asynchronous inputs include the output enable (
OE
), clock
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved
or linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/
LD
) pin in Low
state. Subsequent burst address can be internally
generated by the chip and controlled by the same input pin
ADV/
LD
in High state.
Write cycles are internally self-time and synchronous with
the rising edge of the clock input and when R/
W
is Low.
The feature simplified the write interface. Individual Byte
enables allow individual bytes to be written.
BW1
controls
I/Oa pins;
BW2
controls I/Ob pins;
BW3
controls I/Oc pins;
and
BW4
controls I/Od pins. Cycle types can only be
defined when an address is loaded.
The SRAM operates from a +3.3V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
PRELIMINARY
(August, 2005, Version 0.0)
2
AMIC Technology, Corp.
A67L06181/A67L93361
Pin Configuration
512K X 36
CE
A6
A7
OE
ADV/
LD
BW4
BW3
BW2
BW1
VCC
CEN
A18
VSS
CLK
CE2
CE2
R/W
A17
A8
A8
82
CEN
OE
ADV/
LD
BW2
BW1
VCC
VSS
CLK
R/W
A19
CE2
CE2
NC
NC
A6
A7
CE
A18
1M X 18
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/Oc
8
I/Oc
0
I/Oc
1
VCCQ
VSSQ
I/Oc
2
I/Oc
3
I/Oc
4
I/Oc
5
VSSQ
VCCQ
I/Oc
6
I/Oc
7
VSS
VCC
VCC
VSS
I/Od
0
I/Od
1
VCCQ
VSSQ
I/Od
2
I/Od
3
I/Od
4
I/Od
5
VSSQ
VCCQ
I/Od
6
I/Od
7
I/Od
8
NC
NC
NC
VCCQ
VSSQ
NC
NC
I/Ob
8
I/Ob
7
VSSQ
VCCQ
I/Ob
6
I/Ob
5
VSS
VCC
VCC
VSS
I/Ob
4
I/Ob
3
VCCQ
VSSQ
I/Ob
2
I/Ob
1
I/Ob
0
NC
VSSQ
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
81
A9
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
A10
NC
NC
VCCQ
VSSQ
NC
I/Oa
0
I/Oa
1
I/Oa
2
VSSQ
VCCQ
I/Oa
3
I/Oa
4
VSS
VSS
VCC
ZZ
I/Oa
5
I/Oa
6
VCCQ
VSSQ
I/Oa
7
I/Oa
8
NC
NC
VSSQ
VCCQ
NC
NC
NC
I/Ob
8
I/Ob
7
I/Ob
6
VCCQ
VSSQ
I/Ob
5
I/Ob
4
I/Ob
3
I/Ob
2
VSSQ
VCCQ
I/Ob
1
I/Ob
0
VSS
VSS
VCC
ZZ
I/Oa
7
I/Oa
6
VCCQ
VSSQ
I/Oa
5
I/Oa
4
I/Oa
3
I/Oa
2
VSSQ
VCCQ
I/Oa
1
I/Oa
0
I/Oa
8
A67L06181E
A67L93361E
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A5
A4
A3
A2
A1
A0
A11
A12
A13
A14
A15
A16
A15
MODE MODE
VSS
VCC
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
VSS
VCC
PRELIMINARY
(August, 2005, Version 0.0)
3
AMIC Technology, Corp.
A16
NC
NC
NC
NC
A17
NC
NC
NC
NC
A67L06181/A67L93361
Block Diagram (512K X 36)
ZZ
MODE
MODE
LOGIC
ADV/LD
CEN
CLK
CLK
LOGIC
BURST
LOGIC
ADDRESS
COUNTER
CLR
A0-A18
ADDRESS
REGISTERS
WRITE
ADDRESS
REGISTER
9
BYTEa
WRITE
DRIVER
9
ADV/LD
R/W
BW1
BW2
BW3
BW4
WRITE
REGISTRY
&
CONTROL
LOGIC
BYTEb
WRITE
DRIVER
BYTEc
WRITE
DRIVER
BYTEd
WRITE
DRIVER
9
9
512KX9X4
MEMORY
SENSE
AMPS
OUTPUT
BUFFERS
I/O
s
9
9
ARRAY
9
9
DATA-IN
REGISTERS
CE
CE2
CE2
CHIP
ENABLE
LOGIC
FLOW-THROUGH
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(August, 2005, Version 0.0)
4
AMIC Technology, Corp.
A67L06181/A67L93361
Block Diagram (1M X 18)
ZZ
MODE
MODE
LOGIC
ADV/LD
CEN
CLK
CLK
LOGIC
BURST
LOGIC
ADDRESS
COUNTER
CLR
A0- A19
ADDRESS
REGISTERS
WRITE
ADDRESS
REGISTER
9
WRITE
REGISTRY
&
CONTROL
LOGIC
BYTEa
WRITE
DRIVER
9
1MX9X2
MEMORY
SENSE
AMPS
OUTPUT
BUFFERS
I/O
S
ADV/LD
R/W
BW1
BW2
9
BYTEb
WRITE
DRIVER
9
ARRAY
DATA-IN
REGISTERS
CE
CE2
CE2
CHIP
ENABLE
LOGIC
FLOW-
THROUGH
ENABLE LOGIC
OUTPUT
ENABLE
LOGIC
OE
PRELIMINARY
(August, 2005, Version 0.0)
5
AMIC Technology, Corp.
DSP 与 ARM 处理器
