Changes to Ordering Guide .......................................................... 18
9/99—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
SS
= 0 V, V
A
= V
DD
, V
B
= 0 V, −40°C < T
A
< +85°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS RHEOSTAT MODE
2
Resistor Differential NL
3
Resistor Nonlinearity Error
3
Nominal Resistor Tolerance
4
Resistance Temperature Coefficient
Nominal Resistance Match
Symbol
R-DNL
R-INL
ΔR
AB
ΔR
AB
/ΔT
ΔR/R
AB
Test Conditions/Comments
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
Channel 1 to Channel 2, Channel 3, and
Channel 4, or to Channel 5 and Channel 6;
V
AB
= V
DD
I
W
= 1 V/R, V
DD
= 5 V
Min
−1
−2
−30
AD5204/AD5206
Typ
1
±0.25
±0.5
700
0.25
Max
+1
+2
+30
1.5
Unit
LSB
LSB
%
ppm/°C
%
Wiper Resistance
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
2
Resolution
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance
7
Ax, Bx
Capacitance
7
Wx
Shutdown Current
8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
7
POWER SUPPLIES
Power Single-Supply Range
Power Dual-Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
7, 10
Bandwidth −3 dB
R
W
50
100
Ω
N
DNL
INL
ΔV
W
/ΔT
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
A_SD
I
CM
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
range
V
DD
/V
SS
range
I
DD
I
SS
P
DISS
PSS
BW_10K
BW_50K
BW_100K
THD
W
t
S
e
N_WB
8
−1
−2
Code = 0x40
Code = 0x7F
Code = 0x00
−2
0
V
SS
f = 1 MHz, measured to GND, code = 0x40
f = 1 MHz, measured to GND, code = 0x40
V
A
= V
B
= V
W
= 0, V
DD
= +2.7 V, V
SS
= −2.5 V
V
DD
= 5 V/3 V
V
DD
= 5 V/3 V
R
PULL–UP
= 1 kΩ to 5 V
I
OL
= 1.6 mA, V
LOGIC
= 5 V
V
IN
= 0 V or 5 V
2.4/2.1
±0.25
±0.5
15
−1
1
+1
+2
0
2
V
DD
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
μA
nA
V
V
V
V
μA
pF
V
V
μA
μA
mW
%/%
kHz
kHz
kHz
%
μs
nV/√Hz
45
60
0.01
1
5
0.8/0.6
4.9
0.4
±1
5
V
SS
= 0 V
V
IH
= 5 V or V
IL
= 0 V
V
SS
= −2.5 V, V
DD
= +2.7 V
V
IH
= 5 V or V
IL
= 0 V
ΔV
DD
= 5 V ± 10%
R
AB
= 10 kΩ
R
AB
= 50 kΩ
R
AB
= 100 kΩ
V
A
= 1.414 V rms, V
B
= 0 V dc, f = 1 kHz
V
A
= 5 V, V
B
= 0 V, ±1 LSB error band
R
WB
= 5 kΩ, f = 1 kHz, PR = 0
2.7
±2.3
12
12
0.0002
721
137
69
0.004
2/9/18
9
5.5
±2.7
60
60
0.3
0.005
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage
Rev. D | Page 3 of 20
AD5204/AD5206
Parameter
INTERFACE TIMING CHARACTERISTICS
7, 11, 12
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK-to-SDO Propagation Delay
13
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
2
Data Sheet
Symbol
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH0
t
CSH1
t
CS1
Test Conditions/Comments
Clock level high or low
Min
20
5
5
1
15
40
90
0
0
10
Typ
1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 2 kΩ , C
L
< 20 pF
150
Typicals represent average readings at 25°C and V
DD
= 5 V.
Applies to all VRs.
3
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.
I
W
= V
DD
/R for both V
DD
= 3 V and V
DD
= 5 V.
4
V
AB
= V
DD
, wiper (V
W
) = no connect.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.
6
Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.
7
Guaranteed by design and not subject to production test.
8
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= 5 V.
11
Applies to all parts.
12
See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V
