64-Position OTP Digital Potentiometer
AD5273
FEATURES
64 positions
One-time programmable (OTP)
1
set-and-forget
Resistance setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Compact 8-lead SOT-23 standard package
Ultralow power: I
DD
= 5 μA maximum
Fast settling time: t
S
= 5 μs typical during power-up
I
2
C-compatible digital interface
Computer software
2
replaces microcontroller in
factory programming applications
Wide temperature range: −40°C to +105°C
Low operating voltage: 2.7 V to 5.5 V
OTP validation check function
SCL
SDA
I
2
C INTERFACE
AND
CONTROL LOGIC
FUNCTIONAL BLOCK DIAGRAM
A
W
AD0
AD5273
WIPER
REGISTER
FUSE
LINK
B
V
DD
GND
Figure 1.
APPLICATIONS
System calibrations
Electronics level settings
Mechanical potentiometers and trimmer replacement
Automotive electronics adjustments
Transducer circuit adjustments
Programmable filters up to 6 MHz BW
3
In addition, for applications that program the AD5273 at the
factory, Analog Devices offers device programming software
2
running on Windows® NT, Windows 2000, and Windows XP
operating systems. This software application effectively replaces
any external I
2
C controllers, which in turn enhances the user
system’s time-to-market.
The AD5273 is available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
resistances and in a compact 8-lead SOT-23 standard package.
It operates from −40°C to +105°C.
Along with its unique OTP feature, the AD5273 lends itself
well to general digital potentiometer applications due to its
effective resolution, array resistance options, small footprint,
and low cost.
An AD5273 evaluation kit and software are available. The kit
includes the connector and cable that can be converted for
factory programming applications.
For applications that require dynamic adjustment of resistance
settings with nonvolatile EEMEM, users should refer to the
AD523x and AD525x families of nonvolatile memory digital
potentiometers.
GENERAL DESCRIPTION
The AD5273 is a 64-position, one-time programmable (OTP)
digital potentiometer
4
that employs fuse link technology to
achieve permanent program setting. This device performs the
same electronic adjustment function as most mechanical
trimmers and variable resistors. It allows unlimited adjustments
before permanently setting the resistance values. The AD5273 is
programmed using a 2-wire, I
2
C-compatible digital control.
During write mode, a fuse blow command is executed after the
final value is determined, thereby freezing the wiper position at
a given setting (analogous to placing epoxy on a mechanical
trimmer). When the permanent setting is achieved, the value
does not change, regardless of the supply variations or environ-
mental stresses under normal operating conditions. To verify
the success of permanent programming, Analog Devices, Inc.,
patterned the OTP validation such that the fuse status can be
discerned from two validation bits in the read mode.
1
2
OTP allows unlimited adjustments before permanent setting.
Analog Devices cannot guarantee the software to be 100% compatible to all
systems due to the wide variation in computer configurations.
3
Applies to 1 kΩ parts only.
4
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
03224-001
AD5273
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
One-Time Programming ........................................................... 13
Variable Resistance and Voltage for Rheostat Mode ............. 14
Variable Resistance and Voltage for Potentiometer Mode .... 14
ESD Protection ........................................................................... 15
Terminal Voltage Operating Range.......................................... 15
Power-Up/Power-Down Sequences ......................................... 15
Power Supply Considerations ................................................... 15
Controlling the AD5273 ................................................................ 16
Software Programming ............................................................. 16
I
2
C Controller Programming .................................................... 17
Controlling Two Devices on One Bus ..................................... 18
Applications Information .............................................................. 19
DAC.............................................................................................. 19
Programmable Voltage Source with Boosted Output ........... 19
Programmable Current Source ................................................ 19
Gain Control Compensation .................................................... 19
Programmable Low-Pass Filter ................................................ 20
Level Shift for Different Voltages Operation .......................... 20
RDAC Circuit Simulation Model ............................................. 20
Evaluation Board ............................................................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/10—Rev. G to Rev. H
Changes to OTP Power Supply Parameter in Table 1 .................. 4
Changes to V
DD
Pin Description in Table 3................................... 7
Changes to One-Time Programming Section ............................ 13
Changes to Power Supply Considerations Section, Figure 38 .. 15
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
8/08—Rev. F to Rev. G
Changes to Power Supplies Parameter in Table 1......................... 3
Updated Fuse Blow Condition to 400 ms Throughout ............... 5
1/08—Rev. E to Rev. F
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 7
Inserted Figure 28 ........................................................................... 12
Changes to One-Time Programming Section ............................ 13
Changes to Power Supply Considerations Section..................... 15
Deleted Figure 35 ............................................................................ 15
Changes to Figure 36 ...................................................................... 15
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/05—Rev. D to Rev. E
Changes to Features ..........................................................................1
Changes to Specifications .................................................................3
Changes to Table 3.............................................................................6
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 35 and Figure 37............................................. 15
Changes to DAC Section ............................................................... 19
Changes to Level Shift for Different Voltages
Operation Section........................................................................... 20
Deleted the Resistance Scaling Section ....................................... 20
Deleted the Resolution Enhancement Section ........................... 20
12/04—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Specifications .................................................................3
Changes to Theory of Operation Section.................................... 13
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 35, Figure 36, and Figure 37 ......................... 15
11/03—Rev. B to Rev. C
Changes to SDA Bit Definitions and Descriptions .................... 10
Changes to One-Time Programming (OTP) Section................ 11
Changes to Table III ....................................................................... 11
Changes to Power Supply Considerations .................................. 13
Changes to Figure 8, Figure 9, and Figure 10 ............................. 13
Rev. H | Page 2 of 24
AD5273
10/03—Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to Applications ................................................................... 1
Changes to Specifications ................................................................. 2
Changes to Absolute Maximum Ratings ........................................ 4
Changes to Pin Function Descriptions........................................... 5
Changes to TPC 7, TPC 8, TPC 13, and TPC 14 Captions ......... 7
Deleted TPC 20; Renumbered Successive TPCs ........................... 9
Change to TPC 21 Caption .............................................................. 9
Change to the SDA Bit Definitions and Descriptions ................10
Replaced Theory of Operation Section ........................................11
Replaced Determining the Variable Resistance and
Voltage Section ................................................................................11
Replaced ESD Protection Section ................................................. 12
Replaced Terminal Voltage Operating Range Section ............... 12
Replaced Power-Up Sequence Section ......................................... 12
Replaced Power Supply Considerations Section ......................... 13
Changes to Application Section .................................................... 16
Change to Equation 9 ..................................................................... 17
Deleted Digital Potentiometer Family Selection Guide ............. 19
6/03—Rev. 0 to Rev. A
Change to Specifications .................................................................. 2
Change to Power Supply Considerations Section ....................... 12
Updated Outline Dimensions........................................................ 20
12/02—Revision 0: Initial Version
Rev. H | Page 3 of 24
AD5273
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, V
A
< V
DD
, V
B
= 0 V, −40°C < T
A
< +105°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity
2
10 kΩ, 50 kΩ, 100 kΩ
1 kΩ
Resistor Nonlinearity
2
10 kΩ, 50 kΩ, 100 kΩ
1 kΩ
Nominal Resistance Tolerance
3
10 kΩ, 50 kΩ, 100 kΩ
Nominal Resistance, 1 kΩ
Rheostat Mode Temperature
Coefficient
4
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider
4
Temperature Coefficient
Full-Scale Error
10 kΩ, 50 kΩ, 100 kΩ
1 kΩ
Zero-Scale Error
10 kΩ, 50 kΩ, 100 kΩ
1 kΩ
RESISTOR TERMINALS
Voltage Range
6
Capacitance
7
A, B
Capacitance
7
W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)
8
Input Logic Low (SDA and SCL)
8
Input Logic High (AD0)
Input Logic Low (AD0)
Input Logic Current
Input Capacitance
7
Output Logic Low (SDA)
Three-State Leakage Current
Output Capacitance
7
POWER SUPPLIES
Power Supply Range
OTP Power Supply
8, 9
Symbol
N
R-DNL
R
WB
, V
A
= NC
R
WB
, V
A
= NC
R-INL
R
WB
, V
A
= NC
R
WB
, V
A
= NC
T
A
= 25°C
−0.5
−5
−30
0.8
Wiper = NC
I
W
= V
DD
/R, V
DD
= 3 V or 5 V
+0.10
+2
+0.5
+5
+30
1.6
LSB
LSB
%
kΩ
ppm/°C
Ω
−0.5
−1
+0.05
+0.25
Test Conditions/Comments
Min
Typ
1
Max
6
+0.5
+1
Unit
Bits
LSB
LSB
ΔR
AB
/R
AB
R
AB
(ΔR
AB
/R
AB
)/∆T
R
W
1.2
300
60
100
DNL
INL
(ΔV
W
/V
W
)/ΔT
V
WFSE
−0.5
−0.5
Code = 0x20
Code = 0x3F
−1
−1
−6
−6
0
0
GND
f = 5 MHz, measured to GND,
code = 0x20
f = 1 MHz, measured to GND,
code = 0x20
V
A
= V
B
= V
W
0.7 × V
DD
−0.5
3.0
0
+0.1
10
+0.5
+0.5
0
0
0
0
1
5
V
DD
V
WZSE
Code = 0x00
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
LSB
LSB
V
pF
pF
nA
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
OL
I
OZ
C
OZ
V
DD
V
DD_OTP
25
55
1
V
DD
+ 0.5
0.3 × V
DD
V
DD
0.4
1
0.4
±1
3
2.7
5.5
5.25
5.0
0.1
100
5.5
5.25
5
V
IN
= 0 V or 5 V
0.01
3
V
V
V
V
μA
pF
V
μA
pF
V
V
V
μA
mA
Supply Current
OTP Supply Current
8, 10,11
I
DD
I
DD_OTP
T
A
= 25°C
1 kΩ (DD8), 10 kΩ (DD9)
50 kΩ (DYG), 100 kΩ (DYH)
V
IH
= 5 V or V
IL
= 0 V
T
A
= 25°C, V
DD_OTP
= 5 V
5.0
4.75
Rev. H | Page 4 of 24
AD5273
Parameter
Power Dissipation
12
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
7, 13, 14
Bandwidth, −3 dB
Symbol
P
DISS
PSRR
PSRR
BW_1 kΩ
BW_10 kΩ
BW_50 kΩ
BW_100 kΩ
THD
W
t
S1
t
S2
e
N_WB
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
0.6
400
After this period, the first clock
pulse is generated
Test Conditions/Comments
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
R
AB
= 1 kΩ
R
AB
= 10 kΩ, 50 kΩ, 100 kΩ
R
AB
= 1 kΩ, code = 0x20
R
AB
= 10 kΩ, code = 0x20
R
AB
= 50 kΩ, code = 0x20
R
AB
= 100 kΩ, code = 0x20
V
A
= 1 V rms, R
AB
= 1 kΩ, V
B
= 0 V,
f = 1 kHz
V
A
= 5 V ± 1 LSB error band,
V
B
= 0 V, measured at V
W
V
A
= 5 V ± 1 LSB error band,
V
B
= 0 V, measured at V
W
, V
DD
= 5 V
R
AB
= 1 kΩ, f = 1 kHz, code = 0x20
Applies to all parts
1.3
0.6
1.3
0.6
0.6
Min
−0.3
−0.05
6000
600
110
60
0.05
5
5
3
400
Typ
1
0.5
Max
27.5
+0.3
+0.05
Unit
μW
%/%
%/%
kHz
kHz
kHz
kHz
%
μs
μs
nV/√Hz
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ms
Total Harmonic Distortion
Adjustment Settling Time
Power-Up Settling Time—
After Fuses Blown
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS
7, 14, 15
SCL Clock Frequency
t
BUF
Bus Free Time Between
Stop and Start
t
HD; STA
Hold Time
(Repeated Start)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU; STA
Setup Time for
Start Condition
t
HD; DAT
Data Hold Time
t
SU; DAT
Data Setup Time
t
F
Fall Time of Both SDA and
SCL Signals
t
R
Rise Time of Both SDA and
SCL Signals
t
SU; STO
Setup Time for Stop Condition
OTP Program Time
1
2
50
0.9
0.1
0.3
0.3
Typical values represent average readings at 25°C, V
DD
= 5 V, and V
SS
= 0 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
∆R
WB
/∆T = ∆R
WA
/∆T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.
5
INL and DNL are measured at V
W
. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
W
with the RDAC configured as a
potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating
conditions.
6
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
7
Guaranteed by design; not subject to production test.
8
The minimum voltage requirement on the V
IH
is 0.7 × V
DD
. For example, V
IH
min = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V
DD
.
However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
9
Different from the operating power supply; the power supply for OTP is used one time only.
10
Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.
11
See Figure 28 for the energy plot during the OTP program.
12
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
13
Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
14
All dynamic characteristics use V
DD
= 5 V.
15
See Figure 29 for the location of the measured values.
Rev. H | Page 5 of 24
