32-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5372/AD5373
FEATURES
32-channel DAC in a 64-lead LQFP and 64-lead LFCSP
AD5372/AD5373
1
guaranteed monotonic to 16/14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DV
CC
V
DD
V
SS
AGND DGND
LDAC
n = 16 FOR AD5372
n = 14 FOR AD5373
8
n
X1 REGISTER
n
n
M REGISTER
C REGISTER
n
n
A/B SELECT
REGISTER
8
n
TO
MUX 2s
VREF0
CONTROL
REGISTER
n
14
OFS0
REGISTER
n
OFFSET
DAC 0
BUFFER
BUFFER
GROUP 0
A/B
MUX
MUX
2
n
X2A REGISTER
X2B REGISTER
n
DAC 0
REGISTER
n
DAC 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
A/B
MUX
MUX
2
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
SERIAL
INTERFACE
n
X1 REGISTER
n
n
M REGISTER
C REGISTER
n
n
n
n
X2A REGISTER
X2B REGISTER
n
DAC 7
REGISTER
n
DAC 7
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT7
SIGGND0
14
8
n
X1 REGISTER
STATE
MACHINE
n
n
M REGISTER
C REGISTER
n
n
A/B SELECT
REGISTER
8
n
TO
MUX 2s
OFS1
REGISTER
n
OFFSET
DAC 1
BUFFER
BUFFER
GROUP 1
VREF1
A/B
MUX
MUX
2
n
X2A REGISTER
X2B REGISTER
n
DAC 0
REGISTER
n
DAC 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
A/B
MUX
MUX
2
n
X1 REGISTER
n
n
M REGISTER
C REGISTER
n
n
n
n
X2A REGISTER
X2B REGISTER
n
DAC 7
REGISTER
n
DAC 7
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VOUT15
SIGGND1
AD5372/
AD5373
GROUP 2 TO GROUP 3
ARE IDENTICAL TO GROUP 1
VREF1 SUPPLIES
GROUP 1 TO GROUP 3
VOUT16
TO
VOUT31
05815-001
SIGGND2
SIGGND3
Figure 1.
1
Protected by U.S. Patent No. 5,969,657.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
AD5372/AD5373
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
DAC Architecture....................................................................... 15
Channel Groups.......................................................................... 15
A/B Registers and Gain/Offset Adjustment............................ 16
Load DAC.................................................................................... 16
Offset DACs ................................................................................ 16
Output Amplifier........................................................................ 17
Transfer Function ....................................................................... 17
Reference Selection .................................................................... 17
Calibration................................................................................... 18
Additional Calibration............................................................... 19
Reset Function ............................................................................ 19
Clear Function ............................................................................ 19
BUSY and LDAC Functions...................................................... 19
Power-Down Mode.................................................................... 20
Thermal Shutdown Function ................................................... 20
Toggle Mode................................................................................ 20
Serial Interface ................................................................................ 21
SPI Write Mode .......................................................................... 21
SPI Readback Mode ................................................................... 21
Register Update Rates ................................................................ 21
Channel Addressing and Special Modes ................................. 22
Special Function Mode.............................................................. 23
Applications Information .............................................................. 24
Power Supply Decoupling ......................................................... 24
Power Supply Sequencing ......................................................... 24
Interfacing Examples ................................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
Changes to Absolute Maximum Ratings Section..........................9
Changes to Pin Configuration and Function Descriptions
Section.............................................................................................. 10
Changes to Reset Function Section.............................................. 18
12/07—Rev. 0 to Rev. A
Changes to Table 3.............................................................................6
Changes to AD5373 Transfer Function Section......................... 16
Changes to Calibration Section .................................................... 17
Changes to Table 8.......................................................................... 18
Changes to Register Update Rates Section.................................. 20
Changes to Ordering Guide .......................................................... 25
8/07—Revision 0: Initial Version
REVISION HISTORY
7/11—Rev.
B to Rev. C
Added 64-Lead LFCSP Package........................................Universal
Change to Features Section ............................................................. 1
Change to General Description Section ........................................ 3
Changes to Table 5............................................................................ 9
Added Figure 7; Renumbered Sequentially ................................ 10
Changes to Table 6.......................................................................... 10
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
2/08—Rev. A to Rev. B
Added Table 1.................................................................................... 3
Changes to t
10
Parameter ................................................................. 6
Added t
23
Parameter ......................................................................... 6
Changes to Figure 4.......................................................................... 7
Rev. C | Page 2 of 28
AD5372/AD5373
GENERAL DESCRIPTION
The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead
LQFP and LFCSP packages. The devices provide buffered
voltage outputs with a nominal span of 4× the reference voltage.
The gain and offset of each DAC can be independently trimmed
to remove errors. For even greater flexibility, the device is divided
into four groups of eight DACs. Two offset DACs allow the
output range of the groups to be altered. Group 0 can be adjusted
by Offset DAC 0, and Group 1 to Group 3 can be adjusted by
Offset DAC 1.
The AD5372/AD5373 offer guaranteed operation over a wide
supply range: V
SS
from −16.5 V to −4.5 V and V
DD
from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
Table 1. High Channel Count Bipolar DACs
Model
AD5360
AD5361
AD5362
AD5363
AD5370
AD5371
AD5372
AD5373
AD5378
AD5379
Resolution (Bits)
16
14
16
14
16
14
16
14
14
14
Nominal Output Span
4 × V
REF
(20 V)
4 × V
REF
(20 V)
4 × V
REF
(20 V)
4 × V
REF
(20 V)
4 × V
REF
(12 V)
4 × V
REF
(12 V)
4 × V
REF
(12 V)
4 × V
REF
(12 V)
±8.75 V
±8.75 V
Output Channels
16
16
8
8
40
40
32
32
32
40
Linearity Error (LSB)
±4
±1
±4
±1
±4
±1
±4
±1
±3
±3
The AD5372/AD5373 have a high speed serial interface that is
compatible with SPI, QSPI™, MICROWIRE™, and DSP inter-
face standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All
the outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Rev. C | Page 3 of 28
AD5372/AD5373
SPECIFICATIONS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V;
C
L
= open circuit; R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Full-Scale Error
Gain Error
Zero-Scale Error
2
Full-Scale Error
2
Span Error of Offset DAC
VOUTx Temperature Coefficient
DC Crosstalk
2
REFERENCE INPUTS (VREF0, VREF1)
2
VREFx Input Current
VREFx Range
SIGGND INPUTS (SIGGND0 TO SIGGND3)
2
DC Input Impedance
Input Range
SIGGNDx Gain
OUTPUT CHARACTERISTICS
2
Output Voltage Range
Nominal Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
CLR High Impedance Leakage Current
Input Capacitance
2
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage
Output High Voltage (SDO)
SDO High Impedance Leakage Current
High Impedance Output Capacitance
2
AD5372
1
B Version
16
±4
±1
±10
±10
0.1
1
1
±35
5
100
AD5373
1
B Version
14
±1
±1
±10
±10
0.1
1
1
±35
5
100
Unit
Bits
LSB max
LSB max
mV max
mV max
% FSR
LSB typ
LSB typ
mV max
ppm FSR/°C typ
μV max
Test Conditions/Comments
2
Guaranteed monotonic by design over
temperature
Before calibration
Before calibration
Before calibration
After calibration
After calibration
See the Offset DACS section for details
Includes linearity, offset, and gain drift
Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
Per input; typically ±30 nA
±2% for specified operation
Typically 55 kΩ
±10
2/5
50
±0.5
0.995/1.005
V
SS
+ 1.4
V
DD
− 1.4
−4 to +8
15
±1
2200
0.5
1.7
2.0
0.8
±1
±20
10
0.5
DV
CC
− 0.5
±5
10
±10
2/5
50
±0.5
0.995/1.005
V
SS
+ 1.4
V
DD
− 1.4
−4 to +8
15
±1
2200
0.5
1.7
2.0
0.8
±1
±20
10
0.5
DV
CC
− 0.5
±5
10
μA max
V min/V max
kΩ min
V min/V max
min/max
V min
V max
V min/V max
mA max
mA max
pF max
Ω max
V min
V min
V max
μA max
μA max
pF max
V max
V min
μA max
pF typ
I
LOAD
= 1 mA
I
LOAD
= 1 mA
VOUTx to DV
CC
, V
DD
, or V
SS
JEDEC compliant
DV
CC
= 2.5 V to 3.6 V
DV
CC
= 3.6 V to 5.5 V
DV
CC
= 2.5 V to 5.5 V
Excluding CLR pin
Sinking 200 μA
Sourcing 200 μA
Rev. C | Page 4 of 28
AD5372/AD5373
Parameter
POWER REQUIREMENTS
DV
CC
V
DD
V
SS
Power Supply Sensitivity
2
∆Full Scale/∆V
DD
∆Full Scale/∆V
SS
∆Full Scale/∆DV
CC
DI
CC
I
DD
I
SS
Power-Down Mode
DI
CC
I
DD
I
SS
Power Dissipation (Unloaded)
Junction Temperature
3
1
2
AD5372
1
B Version
2.5/5.5
9/16.5
−16.5/−4.5
−75
−75
−90
2
16
18
−16
−18
5
35
−35
250
130
AD5373
1
B Version
2.5/5.5
9/16.5
−16.5/−4.5
−75
−75
−90
2
16
18
−16
−18
5
35
−35
250
130
Unit
V min/V max
V min/V max
V min/V max
dB typ
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
μA typ
μA typ
μA typ
mW typ
°C max
Test Conditions/Comments
2
DV
CC
= 5.5 V, V
IH
= DV
CC
, V
IL
= GND
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Outputs unloaded, DAC outputs = 0 V
Outputs unloaded, DAC outputs = full scale
Bit 0 in the control register is 1
V
SS
= −8 V, V
DD
= 9.5 V, DV
CC
= 2.5 V
T
J
= T
A
+ P
TOTAL
× θ
JA
Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
Guaranteed by design and characterization; not production tested.
3
θ
JA
represents the package thermal impedance.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; C
L
= 200 pF; R
L
= 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 10 kHz
1
B Version
20
30
1
5
10
100
10
0.2
0.02
250
Unit
μs typ
μs max
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
Test Conditions/Comments
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s
VREF0, VREF1 = 2 V p-p, 1 kHz
Effect of input bus activity on DAC output under test
VREF0 = VREF1 = 0 V
Guaranteed by design and characterization; not production tested.
Rev. C | Page 5 of 28
FPGA/CPLD
