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ADC08351 8-Bit, 42 MSPS, 40 mW A/D Converter
November 2003
ADC08351
8-Bit, 42 MSPS, 40 mW A/D Converter
General Description
The ADC08351 is an easy to use low power, low cost, small
size, 42 MSPS analog-to-digital converter that digitizes sig-
nals to 8 bits. The ADC08351 uses an unique architecture
that achieves 7.2 Effective Bits with a 4.4 MHz input and
42 MHz clock frequency and 6.8 Effective Bits with a 21 MHz
input and 42 MHz clock frequency. Output formatting is
straight binary coding.
To minimize system cost and power consumption, the
ADC08351 requires minimal external components and in-
cludes input biasing to allow optional a.c. input signal cou-
pling. The user need only provide a +3V supply and a clock.
Many applications require no separate reference or driver
components.
The excellent dc and ac characteristics of this device, to-
gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Total
power consumption is reduced to less than 7 mW in the
power-down mode. Furthermore, the ADC08351 is resistant
to latch-up and the outputs are short-circuit proof.
Fabricated on a 0.35 micron CMOS process, the ADC08351
is offered in TSSOP and LLP (a molded lead frame-based
chip-scale package), and is designed to operate over the
industrial temperature range of −40˚C to +85˚C.
n
Single +3V Operation
n
Power Down Feature
n
TRI-STATE Outputs
Key Specifications
j
Resolution
j
Maximum Sampling Frequency
j
ENOB
@
f
CLK
= 42 MHz, f
IN
= 4.4 MHz
j
Guaranteed No Missing Codes
j
Power Consumption
8 Bits
42 MSPS (min)
7.2 Bits (typ)
40 mW (typ); 48 mW (max)
(Excluding Reference Current)
Applications
n
n
n
n
n
n
n
n
n
Video Digitization
Digital Still Cameras
Set Top Boxes
Digital Camcorders
Communications
Medical Imaging
Personal Computer Video
CCD Imaging
Electro-Optics
Features
n
Low Input Capacitance
n
Internal Sample-and-Hold Function
Pin Configuration
20-Pin TSSOP
24-Pin LLP (CSP)
10089501
Top View
10089534
Bottom View
© 2003 National Semiconductor Corporation
DS100895
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ADC08351
Ordering Information
ADC08351CIMTC
ADC08351CIMTCX
ADC08351CILQ
ADC08351CILQX
TSSOP
TSSOP (tape & reel)
LLP (tape & reel - 1, 000 units)
LLP (tape & reel - 4, 500 units)
ADC08351 Block Diagram
10089502
Pin Descriptions and Equivalent Circuits
Pin
No.
17
(17)
Symbol
Equivalent Circuit
(LLP pins in parentheses)
Description
V
IN
Analog signal input. Conversion range is 0.5 V
P-P
to
0.68 V
A
.
14
(14)
V
REF
Positive reference voltage input. Operating range of
this voltage is 0.75V to V
A
. This pin should be
bypassed with a 10 µF tantalum or aluminum
electrolytic capacitor and a 0.1 µF ceramic chip
capacitor.
CMOS/TTL compatible digital input that, when low,
enables the digital outputs of the ADC08351. When
high, the outputs are in a high impedance state.
CMOS/TTL compatible digital clock input. V
IN
is
sampled on the falling edge of CLK input.
CMOS/TTL compatible digital input that, when high,
puts the ADC08351 into the power down mode,
where it consumes minimal power. When this pin is
low, the ADC08351 is in the normal operating mode.
1
(22)
12
(11)
15
(15)
OE
CLK
PD
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2
ADC08351
Pin Descriptions and Equivalent Circuits
(LLP pins in parentheses)
Pin
No.
Symbol
Equivalent Circuit
(Continued)
Description
3 thru
10
(1 thru
8)
D0–D7
Conversion data digital output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are enabled
by bringing the OE pin low.
11, 13
(10,
12)
V
D
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. V
A
and V
D
should have a
common supply and be separately bypassed with a
10 µF tantalum or aluminum electrolytic capacitor and
a 0.1 µF ceramic chip capacitor. See Section 3.0 for
more information.
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC08351.
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. V
A
and V
D
should have
a common supply and be separately bypassed with a
10 µF tantalum or aluminum electrolytic capacitor and
a 0.1 µF ceramic chip capacitor. See Section 3.0 for
more information.
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC08351 package.
2, 20
(21,
23)
DGND
16
(16)
V
A
18, 19
(18,
19)
AGND
3
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ADC08351
Absolute Maximum Ratings
2)
(Notes 1,
Package Dissipation at T
A
= 25˚C
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Soldering Temp., Infrared, 10 sec. (Note 6)
Storage Temperature
(Note 4)
4000V
200V
235˚C
−65˚C to +150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A
, V
D
)
Voltage on Any Input or Output
Pin
Ground Difference
(AGND–DGND)
CLK, OE Voltage Range
Digital Output Voltage (V
OH
, V
OL
)
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
4.2V
−0.3V to 4.2V
Operating Ratings
(Notes 1, 2)
Operating Temperature Range
Supply Voltage (V
A
, V
D
)
Ground Difference
|DGND–AGND|
V
IN
Voltage Range (V
P-P
)
−40˚C T
A
≤
+85˚C
+2.7V to +3.6V
0V to 100 mV
0.5V to 0.68 V
A
±
100 mV
−0.5 to (V
A
+ 0.5V)
V
D
to DGND
±
25 mA
±
50 mA
Converter Electrical Characteristics
The following specifications apply for V
A
= V
D
= +3.0 V
DC
, V
REF
= 2.4V, V
IN
= 1.63 V
P-P
, OE = 0V, C
L
= 20 pF,
f
CLK
= 42 MHz, 50% duty cycle, unless otherwise specified.
Boldface limits apply for T
A
= T
MIN
to T
MAX
:
all other limits T
A
=
25˚C (Notes 7, 8)
Symbol
DC Accuracy
INL
DNL
Integral Non Linearity Error
Differential Non Linearity
Missing Codes
E
Z
E
FS
DP
DG
Zero Scale Offset Error
Full Scale Offset Error
Differential Phase Error
Differential Gain Error
f
CLK
= 20 MHz, Video Ramp Input
f
CLK
= 20 MHz, Video Ramp Input
(CLK LOW)
(CLK HIGH)
−17
−7
1.0
1.5
4
11
7.2
120
At pin 14
0.735
V
A
7.7
PD = Low
PD = High
PD = Low, No Digital Output Load
PD = High
Excluding Reference Current, V
IN
= 0 V
DC
PD = Low (excluding reference current)
PD = High (excluding reference current)
10.5
1
2.9
0.5
13.4
40.2
16
48
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
LSB (max)
LSB (max)
LSB (min)
(max)
mV
mV
Degree
%
pF
pF
kΩ
MHz
V
V
mA
mA
mA
mA
mA
mA (max)
mW (max)
mW
±
0.7
±
0.6
±
1.4
+1.3
−1.0
0
Video Accuracy
Analog Input and Reference Characteristics
C
IN
R
IN
FPBW
V
REF
I
REF
V
IN
Input Capacitance
R
IN
Input Resistance
Full-Power Bandwidth
Reference Input Voltage
Reference Input Current
V
IN
= 1.5V + 0.7 Vrms
Power Supply Characteristics
I
A
I
D
Analog Supply Current
Digital Supply Current
Total Operating Current
Power Consumption (active)
Power Consumption (power
down)
CLK, OE Digital Input Characteristics
V
IH
V
IL
I
IH
I
IL
Logical High Input Voltage
Logical Low Input Voltage
Logical High Input Current
Logic Low Input Current
V
D
= V
A
= 3V
V
D
= V
A
= 3V
V
IH
= V
D
= V
A
= 3.3V
V
IL
= 0V, V
D
= V
A
= 3.3V
4
<
7
2.0
1.0
10
−10
V (min)
V (max)
µA
µA
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