Quick Start
DEMO8763x Demonstration Board for ADC1004S030/040/050
family
Rev. 2.0 — 2 July 2012
Quick Start
Document information
Info
Keywords
Content
DEMO8763x, PCB618-2, Demonstration board, ADC, Converter,
ADC1004S030/040/050
This document describes how to use the demonstration board
DEMO8763x for the analog-to-digital converter ADC1004S030/040/050
family.
Abstract
Overview
Revision history
Rev
2.0
0.1
Date
20120702
20080624
Description
Rebranded.
Initial version.
1. Quick start
1.1 Setup overview
Figure Fig 1
presents the connections to measure DEMO8763x.
P
OWER SUPPLY
. GND
. I = 210 mA
. 12V
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. External clock
. Binary ADC output
. Output enable
. VRB = 1.3 V
DC
. VI+VOFS = 2.485 V
DC
. VRT = 3.67 V
DC
S
YNCHRONIZED
PULSE
GENERATOR
C
LOCK SIGNAL
(CLK)
. TTL/CMOS
LOGIC ANALYZER
Output data
. Acquisition clock
. DO (LSB) to D9 (MSB)
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT SIGNAL
. 2V
pp
sinewave
. AC
F
ILTER
. High-order
. Band pass
Fig 1. DEMO8763x setup
1.2 Power supply
The board is powered with a single 12 V
DC
power supply. Two power supply regulators
are used to supply all the 5V and 3.3V circuitry on the board.
Table 1.
Name
J1
D3
TM3,
TM4
TM1,
TM5
TM2
General power supply
Function
Green connector – Power supply 12 V
DC
/ 210 mA.
PWR green light – It indicates the good supply plugging
GNDA test point – Analog ground
GNDD test point – Digital ground
GNDO test point – Digital output ground
View
1.3 DC voltage adjustments
The ADC1004S030/040/050 allows to adjust the full scale input signal from 1.7V to 2.5V.
Table 2.
Name
P202
TP8
P201
TP6
P1
TP10
DC voltage adjustments
Function
VRT trimmer – TOP reference adjustment
VRT test point – TOP reference value (typ 3.67 V)
VRB trimmer – BOT reference adjustment
VRB test point – BOT reference value (typ 1.3 V)
VOFS trimmer – Input signal DC offset adjustment
VI test point – Input signal (typ DC offset 2.485 V)
View
1.4 Input signals (IN, CLK)
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized together.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
,where M is an odd number of period and N is the number of samples.
Table 3.
Name
J3
J2
K1
Input signals
Function
VI connector – Analog input signal (
50
matching)
CLK connector – Clock input signal (
50
matching)
OSC switch – On-board oscillator activation
View
Oscillator OFF
K3
Oscillator ON
CLK switch – Selection between on-board clock and
external clock
On-board clock
TP2
External clock
CLK test point – Clock used by the device
1.5 Output signals (D0 to D9, IR)
Table 4.
Name
TP11
to
TP20
D2,
TP3
TP31
K2
Output signals
Function
Array connector – ADC digital output (D0 to D9)
View
IR red light and test point – It indicates that the analog
input signal is out of the full scale range
CLK connector – Clock output for data acquisition
TCN switch – 2’s complement output selection
Binary
K4
2’s complement
OEN switch – Output enable selection
Active output
High impedance output
2. Example
2.1 Setup example
GND
E3620A
H
EWLETT
P
ACKARD
Dual output DC power supply
12 V / 210 mA
16500C
H
EWLETT
P
ACKARD
Logic analysis system
Pod 1
8644A
H
EWLETT
P
ACKARD
0.26-1030 MHz synthesized
signal generator
8644A
H
EWLETT
P
ACKARD
0.26-1030 MHz synthesized
signal generator
8 x 50 MHz
8133A
1.0 V
rms
H
EWLETT
P
ACKARD
3GHz pulse generator
Channel 1 (ext / 8)
10 MH
Z
SYNCHRO
50 Msps
0 to 3V
CLKOUT
WBG4,43 / SN5
Bandpass filter
4.43 MHz 4.43 MHz
-0.5 dBFS
2 V
pp
DO to D9
Fig 2. ADC1004S050 hardware setup
PCB设计
