Features
•
1.65V - 1.95V Read/Write
•
High Performance
– Random Access Time – 70 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not
Being Programmed/Erased
– Memory Plane A: 25% of Memory Including Eight 4K Word Sectors
– Memory Plane B: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane C: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane D: 25% of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
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•
•
•
64-megabit
(4M x 16)
Burst/Page
Mode 1.8-volt
Flash Memory
AT49SN6416
AT49SN6416T
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•
•
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1. Description
The AT49SN6416(T) is a 1.8-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 1.8V power supply, making it ideally suited for In-System
programming. The device can be configured to operate in the asynchronous/page
read (default mode) or burst read mode. The burst read mode is used to achieve a
faster data rate than is possible in the asynchronous/page read mode. If the AVD and
the CLK signals are both tied to GND and the burst configuration register is configured
to perform asynchronous reads, the device will behave like a standard asynchronous
Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed
low to latch the page address. In both cases the CLK can be tied to GND.
The AT49SN6416(T) is divided into four memory planes. A read operation can
occur in any of the three planes which is not being programmed or erased. This con-
current operation allows improved system performance by not requiring the system to
wait for a program or erase operation to complete before a read is performed. To fur-
ther increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
3464C–FLASH–2/05
time and let the user read data from or program data to any of the remaining sectors. There is no
reason to suspend the erase or program operation if the data to be read is in another memory
plane.
The VPP pin provides data protection and faster programming times. When the V
PP
input
is below 0.4V, the program and erase functions are inhibited. When V
PP
is at 0.9V or above,
normal program and erase operations can be performed. With V
PP
at 10.0V, the program (Dual-
word Program command) operation is accelerated.
2. Pin Configurations
Pin Name
I/O0 - I/O15
A0 - A21
CE
OE
WE
AVD
CLK
RESET
WP
VPP
WAIT
VCCQ
NC
Pin Function
Data Inputs/Outputs
Addresses
Chip Enable
Output Enable
Write Enable
Address Latch Enable
Clock
Reset
Write Protect
Write Protection and Power Supply for Accelerated Program Operations
WAIT
Output Power Supply
No Connect
2.1
56-ball CBGA (Top View)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
A11
A12
A8 VSS VCC VPP A18
A9
A20 CLK RESET A17
A6
A5
A7
NC
A4
A3
A2
A1
A0
A13 A10 A21 AVD WE A19
A15 A14 WAIT A16 I/O12 WP
VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE
VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE
I/O7 VSS I/O5 VCC I/O3 VCCQ I/O8 VSS
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AT49SN6416(T)
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AT49SN6416(T)
3. Device Operation
3.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going
pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on
the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of
the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever
occurs first. The addresses used in the command sequences are not affected by entering the
command sequences.
3.2
Burst Configuration Command
The Program Burst Configuration Register command is used to program the burst configuration
register. The burst configuration register determines several parameters that control the read
operation of the device. Bit B15 determines whether synchronous burst reads are enabled or
asynchronous reads are enabled. Since the page read operation is an asynchronous operation,
bit B15 must be set for asynchronous reads to enable the page read feature. The rest of the bits
in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the
burst configuration register determine the clock latency for the burst mode. The latency can be
set to two, three, four, five or six cycles. The
“Clock Latency versus Input Clock Frequency”
table
is shown on
page 21.
The
“Burst Read Waveform”
as shown on
page 32
illustrates a clock
latency of four; the data is output from the device four clock cycles after the first valid clock edge
following the high-to-low AVD edge. The B10 bit of the configuration register determines the
polarity of the WAIT signal. The B9 bit of the burst configuration register determines the number
of clocks that data will be held valid (see
Figure 8-1).
The Hold Data for 2 Clock Cycles Read
Waveform is shown on
page 32.
The clock latency is not affected by the value of the B9 bit. The
B8 bit of the burst configuration register determines when the WAIT signal will be asserted.
When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit
B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge
or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether
a continuous or fixed-length burst will be used and also determine whether a four-, eight- or six-
teen-word length will be used in the fixed-length mode. All other bits in the burst configuration
register should be programmed as shown on
page 21.
The default state (after power-up or
reset) of the burst configuration register is also shown on
page 21.
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3464C–FLASH–2/05
3.3
Asynchronous Read
There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads.
The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The out-
puts are put in the high-impedance state whenever CE or OE is high. This dual-line control gives
designers flexibility in preventing bus contention. The data at the address location defined by
A0 - A21 and captured by the AVD signal will be read when CE and OE are low. The address
location passes into the device when CE and AVD are low; the address is latched on the low-to-
high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of
the device. The access time is measured from stable address, falling edge of AVD or falling
edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static
high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to
GND. The asynchronous read diagrams are shown on
page 29.
3.4
Page Read
The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input
is ignored during a page read operation and should be tied to GND. The page size is four words.
During a page read, the AVD signal can transition low and then transition high, transition low and
remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown
in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the
AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD
signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (deter-
mined by A21 - A2) cannot change during a page read operation. The first word access of the
page read is the same as the asynchronous read. The first word is read at an asynchronous
speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads
within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to
GND, the device will behave like a standard asynchronous Flash memory. The page read dia-
grams are shown on
page 30.
3.5
Synchronous Reads
Synchronous reads are used to achieve a faster data rate than is possible in the asynchro-
nous/page read mode. The device can be configured for continuous or fixed-length burst
access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs.
The initial read location is determined as for the AVD pulsed asynchronous read operation; it can
be any memory location in the device. In the burst access, the address is latched on the first
valid clock edge when AVD is low or the rising edge of the AVD signal, whichever occurs first.
The CLK input signal controls the flow of data from the device for a burst operation. After the
clock latency cycles, the data at the next burst address location is read for each following clock
cycle.
Figure 3-1.
Word Boundary
Word D0 - D3
D0 D1
D2
Word D4 - D7
D5
D6 D7
Word D8 - D11
Word D12 - D15
D3 D4
D8 D9 D10 D11 D12 D13 D14 D15
4-word Boundary
16-word Boundary
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AT49SN6416(T)
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AT49SN6416(T)
3.6
Continuous Burst Read
During a continuous burst read, any number of addresses can be read from the memory. When
operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device
may incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory (see
Figure 3-1).
If the starting address is aligned with a 4-word boundary (D0, D4, D8
or D12), there is no delay. If the starting address is not aligned with a 4-word boundary, an out-
put delay is incurred. The delay depends on the starting address (see
Table 3-1).
The delay
takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate
that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and
B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is
driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated
when the CE or OE signal is high.
Table 3-1.
Output Delay
Output Delay
Hold Data for 1 Clock Cycle, B9 = 0
1 Clock Cycle
2 Clock Cycles
3 Clock Cycles
Output Delay
Hold Data for 2 Clock Cycles, B9 = 1
2 Clock Cycle
4 Clock Cycles
6 Clock Cycles
Starting Address
D1, D5, D9, D13
D2, D6, D10, D14
D3, D7, D11, D15
In the
“Burst Read Waveform”
as shown on
page 32,
the valid address is latched at point A. For
the specified clock latency of four, data D11 is valid within 13 ns of clock edge B. The low-to-high
transition of the clock at point C results in D12 being read. The transition of the clock at point D
results in a burst read of D15. The clock transition at point E does not cause new data to appear
on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock transition,
which signifies that the first boundary in the memory has been crossed and that new data is not
available. The clock transition at point F does cause a burst read of data D16 because the WAIT
signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available.
Additional clock transitions, like at point G, will continue to result in burst reads.
3.7
Fixed-length Burst Reads
During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the
device, depending upon the configuration. The device supports a linear burst mode. The burst
sequence is shown on
page 22.
When operating in the linear burst read mode (B7 = 1) with the
burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary in the memory. If the starting address is aligned with a
4-word boundary (D0, D4, D8 or D12), there is no delay. If the starting address is not aligned
with a 4-word boundary an output delay is incurred. The delay depends on the starting address
(see
Table 3-1).
The delay takes place only once, and only if the burst sequence crosses a
16-word boundary. To indicate that the device is not ready to continue the burst, the device will
drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being
presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The
WAIT signal will be tri-stated when the CE or OE signal is high.
The
“Four-word Burst Read Waveform”
on
page 33
illustrates a fixed-length burst cycle. The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid within
13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read.
Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the
read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
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