ATA5749/ATA5749C
Fractional-N PLL Transmitter IC
DATASHEET
Features
●
Fully integrated fractional-N PLL
●
ASK and closed loop FSK modulation
●
Output power up to +12.5dBm from 300MHz to 450MHz
●
Current consumption is scaled by output power programming
●
Fast crystal oscillator start-up time of typically 200µs
●
Low current consumption of typically 7.3mA at 5.5dBm
●
Only one 13.0000MHz crystal for 314.1MHz to 329.5MHz and 424.5MHz to
439.9MHz operation
●
Single ended RF power amplifier output
●
Many software programmable options using SPI
●
●
●
●
Output power from –0.5dBm to +12.5dBm
RF frequency from 300MHz to 450MHz with different crystals
FSK deviation with 396Hz resolution
CLK output frequency 3.25MHz or 1.625MHz
●
Data rate up to 40kbit/s (Manchester)
●
4KV HBM ESD protection including XTO
●
Operating temperature range of –40°C to +125°C
●
Supply voltage range of 1.9V to 3.6V
●
TSSOP10 package
Benefits
●
Robust crystal oscillator with fast start up and high reliability
●
Lower inventory costs and reduced part number proliferation
●
Longer battery lifetime
●
Supports multi-channel operation
●
Wide tolerance crystal possible with PLL software compensation
9128J-RKE-07/15
1.
Description
The Atmel
®
ATA5749 is a fractional-N-PLL transmitter IC for 300MHz to 450MHz operation and is especially targeted for tire
pressure sensor gauges, remote keyless entry, and passive entry and other automotive applications. It operates at data
rates up to 40kbit/s Manchester for ASK and FSK with a typical 5.5dBm output power at 7.3mA. Transmitter parameters
such as output power, output frequency, FSK deviation, and current consumption can be programmed using the SPI
interface. This fully integrated PLL transmitter IC simplifies RF board design and results in very low material costs.
Figure 1-1. Block Diagram
Atmel ATA5749
CLK_DRV
1
4 or 8
Fractional-N-PLL
CLK_ON
2
FREQ[0:14]
FSEP[0:7]
DIV_CNTRL
FSK_mod
SDIN_TXDIN
9
GND
XTO_RDY
XTO Signal
CLK
1
Power
up/down
10
EN
Frac.
Div.
SCK
3
Digital
Control
433_N315
and
Registers
ASK_mod
PFD
8
VS
PWR[0:3]
CP
ANT2
4
7
XTO1
LP
XTO
(FOX)
5
ANT1
PA
VCO
6
XTO2
2
ATA5749/ATA5749C [DATASHEET]
9128J–RKE–07/15
2.
Pin Configuration
Figure 2-1. TSSOP10 Package Pinout
CLK
1
10
EN
SDIN_TXDIN
2
9
GND
Atmel
SCK
3
ATA5749
8
VS
ANT2
4
7
XTO1
ANT1
5
6
XTO2
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
Pin Description
Symbol
CLK
SDIN_TXDIN
SCK
ANT2
ANT1
XTO2
XTO1
VS
GND
EN
Function
CLK output
Serial bus data input and TX data input
Serial bus clock input
Antenna interface
Antenna interface
Crystal/C
LOAD2
connection
Crystal/C
LOAD1
connection
Supply input
Supply GND
Enable input
ATA5749/ATA5749C [DATASHEET]
9128J–RKE–07/15
3
3.
3.1
Functional Description
Fractional-N PLL
The Atmel
®
ATA5749 block diagram is shown in
Figure 1-1 on page 2.
The operation of the PLL is determined by the
contents of a 32-bit configuration register. The 15-bit value FREQ is used with the 1-bit 434_N315 flag to determine the RF
carrier frequency. This results in a user-selectable frequency step size of 793Hz (with 13.000MHz crystal). With this level of
resolution, it is possible to compensate for crystal tolerance by adjusting the value of FREQ accordingly. This enables the
use of lower cost crystals without compromising final accuracy. In addition, software programming of RF carrier frequency
allows this device to be used in some multi-channel applications.
Modulation type is selected with the 1-bit ASK_NFSK flag. FSK modulation is achieved by modifying the divider block in the
feedback loop. The benefit to this approach is that performance- reducing RF spurs (common in applications that create FSK
by “pulling” the load capacitance in the crystal oscillator circuit) are completely eliminated. The 8-bit value FSEP establishes
the FSK frequency deviation. It is possible to obtain FSK frequency deviations from ±396Hz to ±101kHz in steps of ±396Hz.
The PLL lock time is 1280/(external crystal frequency) and amounts to 98.46µs when using a 13.0000MHz crystal. When
added to the crystal oscillator start-up time, a very fast time-to-transmit is possible (typically 300µs). This feature extends
battery life in applications like Tire Pressure Monitoring Systems, where the message length is often shorter than 10ms and
the time “wasted” during start-up and settling time becomes more significant.
3.2
Selecting the RF Carrier Frequency
The fractional divider can be programmed to generate an RF output frequency f
RF
according to the formulas shown in
Table 3-1.
Note that in the case of f
RF ASK
, the FSEP/2 value is rounded down to the next integer value if FSEP is an odd
number.
Table 3-1.
RF Output Parameter Formulas
S434_N315 = LOW
(24 + (FREQ + 0.5)/16384)
f
XTO
(24 + (FREQ + FSEP + 0.5)/16384)
f
XTO
FSEP/32768
f
XTO
(24 + (FREQ + FSEP/2 + 0.5)/16384)
f
XTO
S434_N315 = HIGH
(32.5 + (FREQ + 0.5)/16384)
f
XTO
(32.5 + (FREQ + FSEP + 0.5)/16384)
f
XTO
FSEP/32768
f
XTO
(32.5 + (FREQ + FSEP/2 + 0.5)/16384)
f
XTO
RF Output Parameter
f
RF_FSK_LOW
f
RF_FSK_HIGH
f
DEV__FSK
f
RF ASK
FSEP can take on the values of 1 to 255. Using a 13.000MHz crystal, the range of frequency deviation f
DEV_FSK
is
programmable from ±396Hz to ±101.16kHz in steps of ±396Hz. For example, with FSEP = 100 the output frequency is FSK
modulated with f
DEV_FSK
= ±39.6kHz.
FREQ can take values in the range of values 2500 and 22000. Using a 13.0000MHz crystal, the output frequency f
RF
can be
programmed to 315MHz by setting FREQ[0:14] = 3730, FSEP[0:7] = 100 and S434_N315 = 0. By setting
FREQ[0:14] = 14342, FSEP[0:7] = 100 and S434_N315 = 1, 433.92MHz can be realized.
4
ATA5749/ATA5749C [DATASHEET]
9128J–RKE–07/15
The PA is enabled when the PLL is locked and the configuration register programming is completed. Upon enabling PA at
FSK-mode, the RF output power will be switched on. At ASK mode, the input signal must be additionally set high for RF at
output pins. The output power is user programmable from –0.5dBm to +12.5dBm in steps of approximately 1dB. Changing
the output power requirements, you also modify the current consumption. This gives the user the option to optimize system
performance (RF link budget versus battery life). The PA is implemented as a Class-C amplifier, which uses an open-
collector output to deliver a current pulse that is nearly independent from supply voltage and temperature. The working
principle is shown in
Figure 3-1.
Figure 3-1. Class C Power Amplifier Output
V
ANT1
V
S
I
ANT2
I
Pulse
= (PWR[0:3])
V
S
V
ANT1
Power Meter
C2
L1
ANT1
5
I
ANT2
50Ω
Z
LOPT
ANT2
4
The peak value of this current pulse I
Pulse
is calibrated during Atmel
®
ATA5749 production to about ±20%, which
corresponds to about 1.5dB variation in output power for a given power setting under typical conditions. The actual value of
I
Pulse
can be programmed with the 4-bit value in PWR. This allows the user to scale both the output power and current
consumption to optimal levels.
ASK modulation is achieved by using the SDIN_TXDIN signal where a HIGH on this pin corresponds to RF carrier “ON” and
a LOW corresponds to RF “OFF”. FSK uses the same signal path but HIGH switch on the upper FSK-frequency.
ATA5749/ATA5749C [DATASHEET]
9128J–RKE–07/15
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