design based on the field-proven BCM5324 device. This
integrated 0.13µ-CMOS device combines all the
functions of a high-speed switch system including
packet buffers, PHY transceivers, Media Access
Controllers (MACs), address management, and a
nonblocking switch fabric. It is designed to be fully
compliant with the IEEE 802.3 and IEEE 802.3x
specifications, including the MAC control PAUSE frame,
auto-negotiation and with all industry-standard
Ethernet and Fast Ethernet devices.
The BCM53262M contains 24 full-duplex 10Base-T/
100Base-TX Fast Ethernet transceivers with Advanced
Cable Diagnostics support. Each performs all physical
layer interface functions for 10Base-T Ethernet on
Category 3, 4, or 5 Unshielded Twisted Pair (UTP) cable
and 100Base-TX Fast Ethernet on Category 5 UTP cable.
The BCM53262M has four SGMII interfaces that provide
flexible 10/100/1000Base-TX/FX connectivity. An
additional MAC is included for CPU connection via
RvMII/MII (Rev. A)/GMII (Rev. B) interface.
The BCM53262M has a rich feature set suitable for
streaming VoIP, video, and data traffic for multimedia
applications. The BCM53262M supports up to four QoS
queues per port. Traffic QoS can be assigned based on
Port-ID, MAC Address, 802.1p or DiffServ. Together with
4K entries, 802.1Q VLAN, 802.1x EAPOL protocol
filtering, MAC-based link aggregation with dynamic
failover, per-port bandwidth/rate control, MAC address
locking, and IGMP snooping at Layer 3 allow system
vendors to build advanced L2+ switch systems for the
Multitenant/Multidweller Unit (MTU/MDU)
markets.The BCM53262M provides 70+ on-chip MIB
counters to collect receive and transmit statistics for
each port.
F E A T U RE S
• Ninth-generation L2+ Fast Ethernet switch with four
SGMII interfaces.
– 24-port 10/100 transceivers for TX/EFX.
– Advanced Cable Diagnostic support.
– 25 10/100 MACs.
– Four Gigabit MACs.
– 3-Mbit (384 KB) packet buffer and control memory.
– Management Port with RvMII/MII interface (Rev. A).
– Management Port with RvMII/MII/GMII interface
(Rev. B).
• Nonblocking switch fabric for 24 FE + 4 GbE ports.
• Jumbo frame support up to 2048 bytes.
• Flexible TCAM-based Compact Field Processor for
packet classification and filtering.
• Packet Remarking, VID Replacement.
– 802.1p PCP, DSCP remarking.
• Optimized for managed switch design.
• 802.1p, Port, MAC, Protocol, Customer_VID, and
DiffServ (IPv4/IPv6) based QoS packet classification with
four priority queues.
• Port-based VLAN.
• 802.1Q-based VLAN with 4K entries.
• MAC-based VLAN with 512 entries.
• Protocol-based VLAN with 16 entries.
• VLAN Translation.
• Double tagging.
– UNI/NNI configuration per port for edge access
application.
– QinQ packet transmission through NNI port.
– Programmable global SP_TPID.
– Programmable SP_VID through flexible mapping.
• Link Aggregation support with automatic link fail-over.
• Programmable per-port Bandwidth/Rate control.
• Protected port security feature.
• Port mirroring (Ingress/Egress), IGMP Layer 3. snooping
and MLD snooping.
• Spanning Tree support (802.1d/1s/1w).
• Supports 802.1x EAPOL higher layer protocol.
• Programmable Broadcast, Multicast, and Unknown
Unicast storm control.8K MAC addresses with automatic
learning and aging.
• MDC/MDIO and SPI interfaces.
• 4K-entry Multicast Address table.
• Hardware supports SNMP, RMON.
• Internal oscillator simplifies design and reduces cost.
• JTAG.
• 2.5V and 1.2V, typical power consumption: ~ 4.3W.
• 676-pin PBGA package.
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53262M-DS302-R
July 28, 2011
BCM53262M Data Sheet
Revision History
MIB Snapshot
Auto MDI/MDIX
Auto MDI/MDIX
Auto MDI/MDIX
GMII (Rev. B)/
MII/RvMII
10/100 PHY
a
(Ports 24~31)
10/100 PHY
a
(Ports 32~39)
10/100 PHY
a
(Ports 40~47)
MAC
(24-31)
MAC
(32-39)
MAC
(40-47)
GMAC/MAC
(48)
GMAC (49)
GMAC (50)
GMAC (51)
GMAC (52)
LED
Interface
SPI/EB
Interface
EEPROM
Interface
QoS
Traffic
Aggregation
Port Trunking
802.1X
Secure MAC
Storm
Control
8K L2 MAC
Table
4K VLAN
Table
IGMP
Snooping
4-Mb Shared
Interface
LED
Buffer
ContentAware
Compact Field
Processor
SGMII
Interface
SerDes
X4
LEDs
CPU Interface
93Cx6
a
Broadcom SDK maps these ports to logical ports 0, 1, … and 23 respectively
Figure 1: Functional Block Diagram
BROADCOM
July 28, 2011 • 53262M-DS302-R
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Page 2
BCM53262M Data Sheet
Revision History
R
EVISION
H
ISTORY
Revision
53262M-DS302-R
Date
07/28/11
Change Description
Updated:
•
Table 48: “Hardware Signal Descriptions,” on page 137
•
Table 64: “LED Control Register (Page 00h: Address 5Ah),” on
page 175
•
Table 255: “802.1Q Control 3 Register (Pages: 34h, Address
08h–0Fh),” on page 304
•
Table 291: “Port MIB Registers (Page 68h–84h),” on page 336
Removed:
• Second note in
“Programming Example” on page 86.
Updated:
• Figure 49, ”BCM53262 LED Register Structure Diagram,” on page
113.
• General: Low-power mode is not supported.
Initial release
53262M-DS300-R
04/30/08
BROADCOM
July 28, 2011 • 53262M-DS302-R
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53262M-DS301-R
04/15/09
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Page 3
BCM53262M Data Sheet
Table of Contents
Table of Contents
About This Document...................................................................................................................................32
Purpose and Audience ...........................................................................................................................32
Acronyms and Abbreviations.................................................................................................................32
Data Sheet Information................................................................................................................................35
Section 2: Features and Operation .................................................................................. 36
NNI to NNI ......................................................................................................................................45
UNI to NNI.......................................................................................................................................47
NNI to UNI.......................................................................................................................................48
Link Aggregation...........................................................................................................................................51
Port Mirroring...............................................................................................................................................55
Hash Function ........................................................................................................................................61
FPGA/CPLD
