DISCRETE SEMICONDUCTORS
DATA SHEET
dbook, halfpage
MBD128
BF1102; BF1102R
Dual N-channel dual gate
MOS-FETs
Product specification
Supersedes data of 1999 Jul 01
2000 Apr 11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
FEATURES
Two low noise gain controlled amplifiers in a single
package
Specially designed for 5 V applications
Superior cross-modulation performance during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.
DESCRIPTION
The BF1102 and BF1102R are both two equal dual gate
MOS-FETs which have a shared source pin and a shared
gate 2 pin. Both devices have interconnected source and
substrate; an internal bias circuit enables DC stabilization
and a very good cross-modulation performance at 5 V
supply voltage; integrated diodes between the gates and
source protect against excessive input voltage surges.
Both devices have a SOT363 micro-miniature plastic
package.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
1
2
3
4
5
6
PINNING - SOT363
BF1102; BF1102R
DESCRIPTION
PIN
BF1102
gate 1 (1)
gate 2 (1 and 2)
drain (1)
drain (2)
gate 1 (2)
BF1102R
gate 1 (1)
source (1 and 2)
drain (1)
drain (2)
gate 1 (2)
source (1 and 2) gate 2 (1 and 2)
handbook, halfpage
g2 (1, 2)
6
5
4
g1 (1)
AMP1
d (1)
g1 (2)
1
2
3
BF1102 marking code:
W1.
BF1102R marking code:
W2-.
AMP2
d (2)
s (1, 2)
MBL029
Fig.1 Simplified outline and symbol.
MIN.
TYP.
43
2.8
30
2
MAX.
UNIT
Per MOS-FET unless otherwise specified
V
DS
I
D
P
tot
y
fs
C
ig1-s
C
rss
F
X
mod
T
j
Note
1. T
s
is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2000 Apr 11
2
drain-source voltage
drain current (DC)
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
cross-modulation
operating junction temperature
T
s
102
C;
note 1
I
D
= 15 mA
I
D
= 15 mA
f = 1 MHz
f = 800 MHz
input level for k = 1% at 40 dB AGC
7
40
200
3.6
50
2.8
150
V
mA
mW
mS
pF
fF
dB
dBV
C
36
100
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
T
s
102
C
BF1102; BF1102R
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
drain-source voltage
drain current (DC)
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
7
40
10
10
200
+150
150
V
mA
mA
mA
mW
C
C
65
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
PARAMETER
thermal resistance from junction to soldering point
VALUE
240
UNIT
K/W
handbook, halfpage
250
MGS359
Ptot
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.2 Power derating curve.
2000 Apr 11
3
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
STATIC CHARACTERISTICS
T
j
= 25
C
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
V
G1-S
= V
G2-S
= 0; I
D
= 10
A
BF1102; BF1102R
MIN.
MAX.
15
15
1.5
1.5
1
1.2
20
50
20
UNIT
Per MOS-FET unless otherwise specified
V
(BR)DSS
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-S
I
G2-S
Note
1. R
G1
connects gate 1 to V
GG
= 5 V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C;
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 15 mA; unless otherwise specified.
SYMBOL
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F
X
mod
PARAMETER
T
j
= 25
C
f = 1 MHz
f = 1 MHz; (note 2)
f = 1 MHz
f = 1 MHz
f = 800 MHz; Y
S
= Y
S opt
f
w
= 50 MHz; f
unw
= 60 MHz; (note 3)
input level for k = 1% at 0 dB AGC
input level for k = 1% at 40 dB AGC
Notes
1. Not used MOS-FET: V
G1-S
= 0; V
DS
= 0.
2. Gate 2 capacitance of both MOS-FETs.
3. Measured in test circuit of Fig.20.
85
100
dBV
dBV
CONDITIONS
MIN.
TYP.
MAX.
UNIT
drain-source breakdown voltage
7
6
6
0.5
0.5
0.3
0.3
12
V
V
V
V
V
V
V
mA
nA
nA
gate 1-source breakdown voltage V
GS
= V
DS
= 0; I
G1-S
= 10 mA
gate 2-source breakdown voltage V
GS
= V
DS
= 0; I
G2-S
= 5 mA
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 100
A
V
DS
= 5 V; V
G1-S
= 4 V; I
D
= 100
A
V
G2-S
= 4 V; V
DS
= 5 V; R
G
= 120 k; note 1
V
G1-S
= 5 V; V
G2-S
= V
DS
= 0
V
G2-S
= 5 V; V
G1-S
= V
DS
= 0
Per MOS-FET unless otherwise specified
(note 1)
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
reverse transfer capacitance
noise figure
cross-modulation
36
2
43
2.8
1.6
30
2
50
3.6
7
2.5
50
2.8
mS
pF
pF
pF
fF
dB
2000 Apr 11
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
ALL GRAPHS FOR ONE MOS-FET
BF1102; BF1102R
handbook, halfpage
30
MGS360
VG2-S = 4 V
3.5 V
3V
2.5 V
handbook, halfpage
30
MGS361
ID
(mA)
20
ID
(mA)
2V
20
VG1-S = 1.5 V
1.4 V
1.3 V
1.2 V
10
1.5 V
10
1.1 V
1V
0
0
0.4
0.8
1.2
1.6
1V
2.0
2.4
VG1-S (V)
0
0
2
4
6
8
10
VDS (V)
V
DS
= 5 V.
T
j
= 25
C.
V
G2-S
= 4 V.
T
j
= 25
C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
handbook, halfpage
160
MGS362
IG1
(μA)
120
VG2-S = 4 V
3.5 V
50
handbook, halfpage
|yfs |
(mS)
40
MGS363
VG2-S = 4 V
3.5 V
3V
3V
30
80
2.5 V
20
40
2V
2.5 V
10
2V
0
0
0.5
1
1.5
2
2.5
VG1-S (V)
0
0
10
20
ID (mA)
30
V
DS
= 5 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
Fig.5
Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6
Forward transfer admittance as a function
of drain current; typical values.
2000 Apr 11
5
微控制器 MCU
