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Datasheet

Serial EEPROM Series Standard EEPROM

C BUS EEPROM (2-Wire)

BR24G32-3A

General Description

BR24G32-3A is a 32Kbit serial EEPROM of I

C BUS Interface Method

Features



All controls available by 2 ports of serial clock(SCL) and

serial data(SDA)



Other devices than EEPROM can be connected to the

same port, saving microcontroller port



1.6V to 5.5V Single Power Source Operation most

suitable for battery use



1MHz action is possible(1.7V to 5.5V)



Up to 32 Byte in Page Write Mode



Bit format 4K x 8bit



Self-timed Programming Cycle



Low Current Consumption



Prevention of Write Mistake



WP (Write Protect) Function added



Prevention of Write Mistake At Low Voltage



More than 1 million write cycles



More than 40 years data retention



Noise filter built in SCL / SDA terminal



Initial delivery state FFh

Packages

W(Typ) x D(Typ) x H(Max)

DIP-T8

9.30mm x 6.50mm x 7.10mm

TSSOP-B8

3.00mm x 6.40mm x 1.20mm

SOP8

5.00mm x 6.20mm x 1.71mm

TSSOP-B8M

3.00mm x 6.40mm x 1.10mm

SOP-J8

4.90mm x 6.00mm x 1.65mm

TSSOP-B8J

3.00mm x 4.90mm x 1.10mm

SOP- J8M

4.90mm x 6.00mm x 1.80mm

MSOP8

2.90mm x 4.00mm x 0.90mm

SSOP-B8

3.00mm x 6.40mm x 1.35mm

VSON008X2030

2.00mm x 3.00mm x 0.60mm

VMMP008Z1830

1.85mm x 3.00mm x 0.40mm

Figure 1.

○Product

structure：Silicon monolithic integrated circuit

○This

product has no designed protection against radioactive rays

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BR24G32-3A

Absolute Maximum Ratings

(Ta=25

°C

)

Parameter

Supply Voltage

Symbol

Rating

-0.3 to +6.5

0.45 (SOP8)

0.45 (SOP-J8M)

0.45 (SOP-J8)

0.30 (SSOP-B8)

0.33 (TSSOP-B8)

Permissible

Dissipation

0.33 (TSSOP-B8M)

0.31 (TSSOP-B8J)

0.31 (MSOP8)

0.30 (VSON008X2030)

0.80 (DIP-T8)

0.21 (VMMP008Z1830)

Storage Temperature

Operating Temperature

Input Voltage /

Output Voltage

Junction

Temperature

Electrostatic discharge

voltage

(human body model)

Tstg

Topr

‐

Tjmax

ESD

-65 to +150

-40 to +85

-0.3 to V

+1.0

150

-4000 to +4000

°C

The Max value of Input Voltage/Output Voltage is not over 6.5V.

When the pulse width is 50ns or less, the Min value of Input

Voltage/Output Voltage is not lower than -1.0V.

Junction temperature at the storage condition

Unit

Remark

Derate by 4.5mW/°C when operating above Ta=25°C

Derate by 3.0mW/°C when operating above Ta=25°C

Derate by 3.3mW/°C when operating above Ta=25°C

Derate by 3.1mW/°C when operating above Ta=25°C

Derate by 3.0mW/°C when operating above Ta=25°C

Derate by 8.0mW/°C when operating above Ta=25°C

Derate by 2.1mW/°C when operating above Ta=25°C

Caution:

Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the

absolute maximum ratings.

Memory Cell Characteristics

(Ta=25

°C

, V

=1.6V to 5.5V)

Parameter

Write Cycles

(Note1)

Data Retention

(Note1)

(Note1) Not 100% TESTED

Min

1,000,000

Limit

Typ

Max

Unit

Times

Years

Recommended Operating Ratings

Parameter

Power Source Voltage

Input Voltage

Symbol

Rating

1.6 to 5.5

0 to V

Unit

DC Characteristics

(Unless otherwise specified, Ta=-40

°C

to +85

°C

, V

=1.6V to 5.5V)

Parameter

Input High Voltage 1

Input Low Voltage 1

Input High Voltage 2

Input Low Voltage 2

Output Low Voltage 1

Output Low Voltage 2

Input Leakage Current

Output Leakage Current

Supply Current (Write)

Supply Current (Read)

Standby Current

Symbol

IH1

IL1

IH2

IL2

OL1

OL2

CC1

CC2

Limit

Min

0.7V

-0.3

(Note1)

0.8V

-0.3

(Note1)

-1

Typ

Max

+1.0

+0.3V

+1.0

+0.2V

0.4

0.2

2.0

μA

Unit

μA

Conditions

1.7V≤V

≤5.5V

1.7V≤V

≤5.5V

1.6V≤V

<1.7V

1.6V≤V

<1.7V

=3.0mA, 2.5V≤V

≤5.5V (SDA)

=0.7mA, 1.6V≤V

<2.5V (SDA)

=0 to V

OUT

=0 to V

(SDA)

=5.5V,f

SCL

=1MHz, t

=5ms,

Byte write, Page write

=5.5V,f

SCL

=1MHz

Random read, current read,

sequential read

=5.5V, SDA, SCL=V

A0, A1, A2=GND,WP=GND

(Note1) When the pulse width is 50ns or less, it is -1.0V.

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AC Characteristics

(Unless otherwise specified, Ta=-40

°C

to +85

°C

)

Parameter

Clock Frequency

Data Clock High Period

Data Clock Low Period

SDA, SCL (INPUT) Rise Time

(Note1)

SDA, SCL (INPUT) Fall Time

(Note1)

SDA (OUTPUT) Fall Time

(Note1)

Start Condition Hold Time

Start Condition Setup Time

Input Data Hold Time

Input Data Setup Time

Output Data Delay Time

Output Data Hold Time

Stop Condition Setup Time

Bus Free Time

Write Cycle Time

Noise Spike Width (SDA, SCL)

WP Hold Time

WP Setup Time

WP High Period

(Note1) Not 100% tested

(Note2) At 1.6V≤V

<1.7V

(Note3) At 1.7V≤V

≤5.5V

Symbol

SCL

HIGH

LOW

HD:STA

SU:STA

HD:DAT

SU:DAT

SU:STO

BUF

HD:WP

SU:WP

HIGH:WP

Limits

(1.6V≤V

≤5.5V)

Min

Typ

Max

0.6

1.2

0.6

100

0.1

(Note2)

0.05

(Note3)

0.1

(Note2)

0.05

(Note3)

0.6

1.2

1.0

0.1

1.0

400

0.3

0.9

0.05

Limits

(1.7V≤V

≤5.5V)

Min

Typ

Max

0.30

0.5

0.25

0.20

0.05

0.25

0.5

1.0

0.1

1.0

1000

0.12

0.45

0.05

Unit

kHz

µs

AC Characteristics Condition

Parameter

Load Capacitance

SDA, SCL (INPUT) Rise Time

SDA, SCL (INPUT) Fall Time

Input Data Level

Input/Output Data Timing Reference Level

Symbol

Conditions

100

0.2V

/0.8V

0.3V

/0.7V

Unit

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Serial Input / Output Timing

SCL

70%

30%

70% 70%

30%

tF1

tHIGH

70%

30%

70%

30%

tHD:STA

70%

30%

70%

tLOW

tSU:DAT

tHD:DAT

70%

30%

SDA

(入力)

(INPUT)

SDA

(出力)

(OUTPUT)

tBUF

tPD

70%

30%

tDH

70%

30%

○Input

read at the rise edge of SCL

○Data

output in sync with the fall of SCL

tF2

Figure 2-(a). Serial Input / Output Timing

SCL

70%

tSU:STA

SDA

70%

30%

tHD:STA

tSU:STO

30%

START CONDITION

STOP CONDITION

Figure 2-(b). Start-Stop Bit Timing

SCL

SDA

write data

(n-th address)

ACK

70%

tWR

STOP CONDITION

START CONDITION

Figure 2-(c). Write Cycle Timing

SCL

70%

DATA(1)

SDA

DATA(n)

ACK

70%

tWR

30%

tSU:WP

tHD:WP

STOP CONDITION

Figure 2-(d). WP Timing at Write Execution

SCL

DATA(1)

SDA

DATA(n)

ACK

tHIGH:WP

ACK

70%

tWR

70%

Figure 2-(e). WP Timing at Write Cancel

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Block Diagram

32Kbit

EEPROM

array

8bit

Address

Decoder

Word

Address

Data

VCC

12bit

START

STOP

A2 3

Control Circuit

ACK

SCL

GND 4

High Voltage

Generating Circuit

Power Source

Voltage Detection

SDA

Figure 3. Block Diagram

Pin Configuration

(TOP VIEW)

GND

BR24G32-3A

8 VCC

6 SCL

5 SDA

Pin Descriptions

Terminal

Name

GND

SDA

SCL

VCC

Input/

Output

Input

Input/

output

Input

Descriptions

Slave address setting

(Note1)

Slave address setting

(Note1)

Slave address setting

(Note1)

Reference voltage of all input / output, 0V

Serial data input serial data output

Serial clock input

Write protect terminal

Connect the power source.

(Note1) A0,A1 and A2 are not allowed to use as open.

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