Not Recommended for New Design
CAT524
Quad Digitally Programmable Potentiometer (DPP) with
256 Taps and Microwire Interface
FEATURES
Four 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
Common reference inputs
Buffered wiper outputs
Non-volatile NVRAM memory wiper storage
Output voltage range includes both supply rails
4 independently addressable buffered
output wipers
1 LSB accuracy, high resolution
Serial Microwire-like interface
Single supply operation: 2.7V - 5.5V
Setting read-back without effecting outputs
DESCRIPTION
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for self-
calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are
not lost when the device is powered down and are
automatically reinstated when power is returned.
Each wiper can be dithered to test new output values
without effecting the stored settings, and stored
settings can be read back without disturbing the
DPP’s output.
The CAT524 is controlled with a simple 3-wire serial,
Microwire-like interface. A Chip Select pin allows
several devices to share a common serial interface.
Communication back to the host controller is via a
single serial data line thanks to the Tri-Stated CAT524
Data Output pin. A RDY/BSY output working in
¯¯¯¯
concert with an internal low voltage detector signals
proper operation of the non-volatile NVRAM memory
Erase/Write cycle.
The CAT524 is available in the 0ºC to 70ºC
commercial and -40ºC to 85ºC industrial operating
temperature ranges. Both 14-pin plastic DIP and
SOIC packages are offered.
For Ordering Information details, see page 14.
APPLICATIONS
Automated product calibration.
Remote control adjustment of equipment
Offset, gain and zero adjustments in self-
calibrating and adaptive control systems.
Tamper-proof calibrations.
DAC (with memory) substitute
PIN CONFIGURATION
PDIP 14-Lead (L)
SOIC 14-Lead (W)
V
DD
CLK
RDY/¯¯¯¯
BSY
CS
DI
DO
PROG
1
2
3
14
13
12
V
REFH
V
OUT1
V
OUT2
V
OUT3
V
OUT4
V
REFL
GND
4
CAT524
11
5
6
7
10
8
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2006 Rev. I
CAT524
Not Recommended for New Design
FUNCTIONAL DIAGRAM
V
DD
1
RDY/BSY
3
V
REFH
14
WIPER CONTROL REGISTERS AND NVRAM
PROG
7
24kΩ
PROGRAM
CONTROL
+
–
24kΩ
13
V
OUT1
DI
CLK
CS
5
2
4
SERIAL
CONTROL
+
–
12
V
OUT2
24kΩ
+
–
11
V
OUT2
24kΩ
+
–
10
V
OUT2
CAT524
8
GND
SERIAL
DATA
OUTPUT
REGISTER
6
DO
9
V
REFL
Doc. No. MD-2006 Rev. I
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT524
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Supply Voltage
V
DD
to GND
Inputs
CLK to GND
CS to GND
DI to GND
¯¯¯¯
RDY/BSY to GND
PROG to GND
V
REFH
to GND
V
REFL
to GND
Ratings
-0.5 to +7
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
Units
V
Parameters
Outputs
D
0
to GND
V
OUT
1– 4 to GND
Operating Ambient Temperature
Commercial
(‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 sec max)
Ratings
-0.5 to V
DD
+0.5
-0.5 to V
DD
+0.5
Units
V
V
V
V
V
V
V
V
V
0 to +70
-40 to +85
+150
-65 to +150
+300
°C
°C
°C
°C
°C
RELIABILITY CHARACTERISTICS
Symbol
V
ZAP(2)
I
LTH(2)(3)
Parameter
ESD Susceptibility
Latch-Up
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
2000
100
Max
Units
V
mA
POWER SUPPLY
Symbol
I
DD1
I
DD2
V
DD
Parameter
Supply Current (Read)
Supply Current (Write)
Operating Voltage Range
Conditions
Normal Operating
Programming, V
DD
= 5V
V
DD
= 3V
Min
—
—
—
2.7
Typ
400
1600
1000
—
Max
600
2500
1600
5.5
Units
µA
µA
µA
V
LOGIC INPUTS
Symbol
I
IH
I
IL
V
IH
V
IL
Parameter
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
Conditions
V
IN
= V
DD
V
IN
= 0V
Min
—
—
2
0
Typ
—
—
—
—
Max
10
-10
V
DD
0.8
Units
µA
µA
V
V
LOGIC OUTPUTS
Symbol
V
OH
V
IL
Parameter
High Level Output Voltage
Low Level Output Voltage
Conditions
I
OH
= -40µA
I
OL
= 1mA, V
DD
= +5V
I
OL
= 0.4mA, V
DD
= +3V
Min
V
DD
-0.3
—
—
Typ
—
—
—
Max
—
0.4
0.4
Units
V
V
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2006 Rev. I
CAT524
Not Recommended for New Design
POTENTIOMETER CHARACTERISTICS
V
DD
= +2.7V to +5.5V, V
REFH
= V
DD
, V
REFL
= 0V, unless otherwise specified
Symbol
R
POT
Parameter
Potentiometer Resistance
R
POT
to RPOT Match
Pot Resistance Tolerance
Voltage on V
REFH
pin
Voltage on V
REFL
pin
Resolution
INL
DNL
R
OUT
I
OUT
TC
RPOT
C
H
/C
L
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Potentiometer Capacitances
300
8/8
2.7
0
0.4
0.5
0.25
1
0.5
10
3
Conditions
See note 3
—
Min
Typ
24
±0.5
±1
±20
V
DD
V
DD
- 2.7
Max
Units
kΩ
%
%
V
V
%
LSB
LSB
Ω
mA
ppm/ºC
pF
AC ELECTRICAL CHARACTERISTICS
V
DD
= +2.7V to +5.5V, V
REFH
= V
DD
, V
REFL
= 0V, unless otherwise specified
Symbol
Digital
t
CSMIN
t
CSS
t
CSH
t
DIS
t
DIH
t
DO1
t
DO0
t
HZ
t
LZ
t
BUSY
t
PS
t
PROG
t
CLK
H
t
CLK
L
f
C
Analog
t
DS
DPP Settling Time to 1 LSB
C
LOAD
= 10pF, V
DD
= +5V
C
LOAD
= 10pF, V
DD
= +3V
—
—
3
6
10
10
µs
µs
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
C
L
= 100pF
(1)
150
100
0
50
50
—
—
—
—
—
150
700
500
300
DC
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
—
—
—
—
—
150
150
—
—
5
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
Parameter
Conditions
Min
Typ
Max
Units
Notes:
(1) All timing measurements are defined at the point of signal crossing V
DD
/ 2.
(2) These parameters are periodically sampled and are not 100% tested.
(3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between V
REFH
and V
REFL
of 6kΩ
+20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.
4
Doc. No. MD-2006 Rev. I
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
TIMING
MIN/MAX
FROM
TO
to
1
2
3
4
5
PARAM
NAME
tCLK H
tCLK H
Rising CLK edge tofalling CLK edge
Min
CLK
t CLK L
Falling CLK edge to CLKrising edge
t CSH
tCLK L
tCSS
tCSH
Falling CLK edge f r last data bit (DI)
o
to falling CS edge
Rising CS edge to ne rising CLK edge
xt
Min
Min
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
A.C. TIMING DIAGRAM
t CSS
Min
CS
tCSMIN
tDIS
tCSMIN
Falling CS edge torising CS edge
Data valid to first rising CLK
edge after CS = high
Min
Min
Not Recommended for New Design
tDIS
DI
tDIH
tDIH
tDO0
tLZ
Rising CLK edge to end of datavalid
Rising CLK edge to D0 = lo
w
Rising CS edge to D0 becoming high
e
low impedance (activ output)
Min
Max
(Max)
5
tDO0
tHZ
t DO1
tPS
tPROG
tBUSY
1
2
3
4
5
tLZ
DO
tDO1
tHZ
Rising CLK edge to D0 = high
Falling CS edge to D0 becoming high
impedance (T
ri-State)
tPS
Rising PROG edge to next rising
CLK edge
tPROG
Rising PROG edge to falling
PROG edge
t BUSY
Falling CLK edge after PR
OG=H
to
rising RD
Y/BSY edge
Max
(Max)
PROG
Min
Min
RDY/BSY
Max
Doc. No. MD-2006 Rev. I
to
CAT524
