Easy memory expansion is provided by active LOW chip en-
ables (CE
1
, CE
2
) and three-state drivers. They have an auto-
matic power-down feature, reducing the power consumption
by 60% when deselected.
Writing to the device is accomplished when the chip enable
(CE
1
, CE
2
) and write enable (WE) inputs are both LOW. Data
on the four input pins (I
0
through I
3
) is written into the memory
location specified on the address pins (A
0
through A
13
).
Reading the device is accomplished by taking the chip enables
(CE
1
, CE
2
) LOW while write enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data out-
put pins.
The output pins stay in high-impedance state when write en-
able (WE) is LOW (7C162A only), or one of the chip enables
(CE
1
, CE
2
) are HIGH.
A die coat is used to insure alpha immunity.
Functional Description
The CY7C161A and CY7C162A are high-performance CMOS
static RAMs organizes as 16,384 by 4 bits with separate I/O.
Logic Block Diagram
I
o
I
1
I
2
I
3
Pin Configurations
DIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
I
0
I
1
CE
1
OE
GND
1
2
3
28
27
26
V
CC
A
4
A
3
A
2
A
1
A
0
I
3
I
2
O
3
O
2
O
1
O
0
WE
CE
2
A
3
A
4
A
5
A
6
A
7
A
8
I
0
I
1
CE
1
LCC
Top View
A2
A1
A0
VCC
A13
3 2 1 28 27
4
26 A
12
5
25 A
11
6
24 A
10
7
23 A
9
8 7C162A 22 I
3
9
21 I
2
10
20 O
3
11
19 O
2
12
18 O
1
1314151617
OE
GND
CE2
WE
O0
C161A–3
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
ROW DECODER
O
0
SENSE AMPS
256 x 256
ARRAY
O
1
O
2
O
3
4
25
5
24
6
23
7C161A
7
22
7C162A
8
21
9
20
10
19
11
18
12
17
13
16
14
15
COLUMN DECODER
POWER
DOWN
C161A–2
CE
1
CE
2
7C162A ONLY
A
8
A
9
A
10
A
11
A
12
A
13
WE
OE
7C161A ONLY
C161A–1
Selection Guide
[1]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
7C161A-15
7C162A-15
15
160
40/20
7C161A-20
7C162A-20
20
100
40/20
7C161A-25
7C162A-25
25
7C161A-35
7C162A-35
35
100
30/20
Military
Military
Shaded area contains advanced information.
Note:
1. For commercial specifications, see the CY7C161/CY7C162 datasheet
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
May 1986 - Revised December 1994
CY7C161A
CY7C162A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
............................................ –0.5V to +7.0V
DC Input Voltage ......................................... –0.5V to +7.0V
[2]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Military
[3]
]
Ambient
Temperature
–55
°
C to +125
°
C
V
CC
5V
±
10%
Electrical Characteristic
s
Over the Operating Range
[4]
7C161A-15
7C162A-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[5]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
Automatic CE
Power-Down Current
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.
I
OUT
= 0 mA
Max. V
CC
, CE > V
IH,
Min. Duty Cycle=100%
Max. V
CC
,
CE
1
> V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V
or V
IN
< 0.3V
Military
Military
Military
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
0.8
+5
+5
-350
160
40
20
2.2
-0.5
–5
–5
Max.
7C161A-20
7C162A-20
Min.
2.4
0.4
V
CC
0.8
+5
+5
-350
100
40
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Shaded area contains advanced information.
Notes:
2. Minimum voltage is equal to
−3.0V
for pulse durations less than 30 ns.
3. T
A
is the “instant on” case temperature.
2
CY7C161A
CY7C162A
3
CY7C161A
CY7C162A
Electrical Characteristics
Over the Operating Range
[4]
(continued)
7C161A-25
7C162A-25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[5]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
Automatic CE
Power-Down Current
[2]
7C161A-35
7C162A-35
Min.
2.4
Max.
0.4
2.2
–0.5
–5
–5
V
CC
0.8
+5
+5
–350
100
30
20
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
Max.
0.4
2.2
–0.5
GND < V
I
< V
CC
GND < V
I
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA
Max. V
CC
, CE > V
IH,
Min. Duty Cycle=100%
Max. V
CC
,
CE
1
> V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V
or V
IN
< 0.3V
Military
Military
Military
–5
–5
V
CC
0.8
+5
+5
–350
100
40
20
6]
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
4. See the last page of this specification for Group A subgroup testing information.
5. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
6. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R1 481Ω
ALL INPUT PULSES
3.0V
R2
255Ω
C161A–4
C161A–5
R2
255Ω
GND
10%
90%
90%
10%
< 5 ns
< 5 ns
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
4
CY7C161A
CY7C162A
]
Switching Characteristics
Over the Operating Range
[4, 7,8]
7C161A-15
7C162A-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
DWE
t
ADV
t
DCE
Read Cycle Time
Address to Data Valid
Output Hold from
Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
OE HIGH to HIGH Z
CE LOW to Low Z
[9]
7C161A-20
7C162A-20
Min.
20
Max.
7C161A-25
7C162A-25
Min.
25
Max.
7C161A-35
7C162A-35
Min.
35
Max.
Unit
ns
35
5
ns
ns
35
15
3
12
5
15
0
20
25
25
25
0
0
20
15
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
30
30
35
ns
ns
ns
ns
Description
Min.
15
Max.
15
3
15
7
0
8
3
8
0
15
15
10
10
0
0
10
7
0
3
7
15
15
15
20
15
15
0
0
15
10
0
5
0
5
3
5
20
5
20
10
3
8
5
8
0
20
20
20
20
0
0
15
10
0
5
7
20
20
20
25
25
12
10
10
20
CE HIGH to High Z
[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write
End
Address Hold from Write
End
Address Set-Up to Write
Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to
Low Z
[9]
(7C162A)
WE LOW to
High Z
[9,10]
(7C162A)
WE LOW to
Data Valid (7C161A)
Data Valid to Output Valid
(7C161A)
CE LOW to Data Valid
(7C161A)
WRITE CYCLE
[11]
7
25
20
25
Shaded area contains advanced information.
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
8. Both CE
1
and CE
2
are represented by CE in the Switching Characteristics and Waveforms sections.
9. At any given temperature and voltage condition, t
HZ
is less than t
LZ
for any given device.
10. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±500
mV from steady-state voltage.
11. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
LOW, and WE LOW. Both signals must be LOW to initiate a write and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
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