16 Megabit 3.3 Volt High Speed SRAM
DP3S512X32MKY5
PRELIMINARY
DESCRIPTION:
The DP3S512X32MKY5 is the 512K x 32 SRAM module that
utilize the new and innovative space saving TSOP stacking
technology. The module is constructed of four 512K x 8
SRAM’s that are configured as 512K x 32.
The DP3S512X32MKY5 provides for a compatible upgrade
path to lower density compatible modules. The module
features high speed access times with common data inputs
and outputs.
PIN-OUT DIAGRAM
FEATURES:
•
Organizations Available:
512K x 32, 1Meg x 16 or 2 Meg x 8
•
Access Times: 12, 15, 17ns
•
Fully Static Operation
- No clock or refresh required
•
Single +3.3V Power Supply, ±10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Package: 72-Pin TSOP Stack
PIN NAMES
A0 - A18
I/O0 - I/O31
CE0 - CE3
WE
OE
V
DD
VSS
N.C.
Address
Data Input / Output
Low Chip Enables
Write Enable
Output Enable
Power (+3.3V)
Ground
No Connect
FUNCTIONAL BLOCK DIAGRAM
30A190-14
REV. A
This document contains information on a product presently under development at Dense-Pac Microsystems, Inc.
Dense-Pac reserves the right to change products or specifications herein without prior notice.
1
DP3S512X32MKY5
PRELIMINARY
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
V
DD
V
IH
V
IL
T
A
Characteristic
TRUTH TABLE
Unit
V
V
V
ºC
Mode
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
C
Operating
Temperature
CI
Min.
3.0
2.0
-0.3
2
0
-40
Typ.
3.3
Max.
3.6
V
DD
+0.3
0.8
+70
+85
+25
+25
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
CEn
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
I/O Pin
HIGH-Z
HIGH-Z
D
OUT
D
IN
Supply Current
Standby
Active
Active
Active
X = Don’t Care
L = LOW
CAPACITANCE
4
:
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
T
A
= +25ºC, F = 1.0MHz
Max.
Unit
35
15
35
35
15
pF
ABSOLUTE MAXIMUM RATING
3
Condition
Symbol
T
STC
T
BIAS
V
IN2
= 0V
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
Max.
-65 to +150
-55 to +125
-0.5 to +4.6
-0.5 to +4.6
Unit
ºC
ºC
V
V
DC OUTPUT CHARACTERISTICS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
AC TEST CONDITIONS
0V to 3.0V
5ns*
Symbol
V
OH
V
OL
Parameter
HIGH Voltage
LOW Voltage
Conditions
I
OH
= -4mA
I
OL
=8mA
Min.
2.4
Max.
0.4
Unit
V
V
1.5V
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+3.3V
OUTPUT LOAD
Load
1
2
C
L
30pF
5pF
Parametric Measured
319Ω
D
OUT
C
L
*
353Ω
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
V
OL
V
OH
Characteristics
DC OPERATING CHARACTERISTICS:
Test Condition
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD ,
CE or OE = V
IH
or WE = V
IL
Cycle = min., Duty = 100%,
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
X8
X16
X32
Over Operating Ranges
Min.
-8
-2
Max.
+8
+2
355
510
820
40
200
0.4
2.4
mA
mA
V
V
mA
Unit
µA
µA
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Standby Current
Standby Current (TTL)
Output LOW Voltage
Output HIGH Voltage
Note:
Typical measurements made at +25°C. Cycle = min., V
DD
= 5.0V.
2
30A190-14
REV. A
Dense-Pac Microsystems, Inc.
PRELIMINARY
DP3S512X32MKY5
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
No.
1
2
3
4
5
6
7
8
9
Symbol
t
RC
t
AA
t
CO
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Parameter
10ns
Min.
Max.
Min.
Over Operating Ranges
15ns
Max.
Min.
Max.
12ns
12
10
10
5
12
12
6
3
0
5
5
0
0
3
6
6
3
0
0
0
3
15
Unit
ns
Read Cycle Time
Address Cycle Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output in LOW-Z
4, 6
Output Enable to Output in LOW-Z
4, 5
Chip Enable to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
10
15
15
7
ns
ns
ns
ns
ns
3
0
0
0
3
7
7
ns
ns
ns
AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE:
No.
10
11
12
13
14
15
16
17
18
19
20
Symbol
t
WC
t
AW
t
CW
t
SA
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
10ns
Min.
Max.
Min.
Over Operating Ranges
6, 7
12ns
Max.
Min.
15ns
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Setup Time *
Write Pulse Width (OE High)
Write Pulse Width (OE Low)
Write Recovery Time
Write Enable to Output in HIGH
4, 5
Data to Write Time Overlap
Data Hold Time form Write Time
Output Active from End of Write
4, 5
10
7
7
0
7
10
0
0
5
0
3
5
12
8
8
0
8
12
0
0
6
0
3
6
15
10
10
0
10
14
0
0
7
0
3
7
ns
ns
ns
ns
* Valid for both Read and Write Cycles.
READ CYCLE 1:
Address Controlled WE is HIGH CE and OE are LOW.
ADDRESS
DATA I/O
30A190-14
REV. A
3
DP3S512X32MKY5
PRELIMINARY
Dense-Pac Microsystems, Inc.
READ CYCLE :
CE is Controlled. WE is HIGH.
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
OE Clock.
ADDRESS
CE
CE
WE
DATA IN
DATA OUT
4
30A190-14
REV. A
Dense-Pac Microsystems, Inc
.
PRELIMINARY
DP3S512X32MKY5
WRITE CYCLE 2:
OE is LOW.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
30A190-14
REV. A
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